LOSTCIRCUITS

Table of Content

Main Page
Standard CMOS settings

Real Time System Clock
IDE Devices
IDE autodetection
Floppy drives (n/a)
Halt On
Video Mode (VGA)

Advanced Chipset Features
Memory timing and performance settings

A short intro to SDRAM, penalty cycles and latencies
SDRAM CAS Latency, CAS; often described as DRAM cycle time
SDRAM tRAS-to-CAS Delay, tRCD; often described as Bank X/Y DRAM timing
SDRAM SRAS Precharge Delay: tRP
Weighting of different latencies

The Pipelines Behind Memory Latencies
Indefinite RAS-To-CAS delay in Open Page Policy
Pipeline Stages and Switches for Programmable CAS latency
Wrong BIOS displays as an excuse to over-rate memory

Bank cycle time tRC (SDRAM active to precharge time), tRAS
tRAS violation as a cause of data corruption
Refresh Interval
SDRAM PH limit
SDRAM idle cycle limit
Bank interleaving

ALi MAGiK1 default BIOS settings

Failsafe, Slow, Normal, Fast, Ultra, UltraII
RW Turnaround
Highway Read
DDR Read Path Short Latency Mode
tDPL
MWB Write Buffer Timeout Flush
Page Life Timer Enable
Enhance Page Mode Timer
DRAM refresh Queue

VIA Apollo Pro266 and KT266 / 333 / 400 Specific Settings
DRAM CMD Rate

Performance vs. stability considerations
KT333 and KT400 latencies
Synchronous vs. Asynchronous Operation
Fake BIOS Settings Allow Cheats by Memory Vendors

Real life situations and settings
"Award v6.00 PG" standard settings analysis
Benchmarks
CAS-Delay (CAS latency, in most VIA chipset BIOS falsely described as DRAM cycle time)
SPD (Serial Presence Detect), Lies and Manufacturer Codes 9.shtml

DRAM clock
Intel BX / AMD 751 Irongate
VIA chipset family
Intel i815(E) chipset
i815 Bank limitiation and its impact on the memory bus frequency
Intel i850 chipset, RDRAM timing

Other memory and Bus timing settings
DRAM read latch delay (VIA chipset only)
CPU-DRAM back-to-back transaction
Memory Hole
IOQ (4 level)
Read Around Write
PCI Dynamic Bursting sometimes called Byte Merge
PCI-to-DRAM Prefetch
CPU-to-PCI write buffer
High Priority PCI mode
PCI Master Read Caching
Delayed Transaction / PCI 2.1 support / passive release

Pentium 4-specific settings
CPU Fast String
CPU OPCode

i850 Dual Channel Rambus
RDRAM Pool B State

System BIOS cacheable
Video RAM Cacheable
Initial Display
AGP Aperture size
AGP-4X mode
Video Memory Cache Mode

I815 specific settings
SDRAM bank closing policy

Other settings
IRQ Routing and PnP OS installed
PCI-latency timer
PCI / DIMM Clck AutoDetect
Spread Spectrum Modulation

Known Bugs

footnote

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