Navigate: Advice Beginners BIOS Guide CPUs Links Mainboards Memory Network Storage Video/Sound Cards Contact Forum SiteMap Sponsors Home PC Hardware from Made-in-China.com Search: Enter your search terms   Web www.lostcircuits.com Submit search form	.
Prices:

CPU-DRAM back-to-back transaction

There are several ways of how the CPU can get the data, the most efficient is the prefetch mode as explained in our K6-X articles almost 2 years ago. Back-to-back mode means that there are address reads alternating with page hits. One example is the full speed cache of the Cu-mine which operates in back-to-back mode, meaning that data transfer effectively happens only at ½ clock speed but it also means that there are very low latencies involved, if any (zero wait states). Similarly, there is the possibility of running the CPU-SDRAM interface in back-to-back mode, that is with zero wait states between consecutive burst writes / reads.

Several Legacy ISA cards require a fixed base memory address between 15 and 16M in the system memory. In order to reserve this space for these cards, a so-called memory hole has been created, preventing other devices from occupying this space. Most of these Legacy ISA cards have become obsolete and thus, it is recommended to disable the memory hole.

There is one exception, though. In some cases, sound cards like the Diamond MX300 or the Creative Labs Soundblaster cause conflicts with other devices, particularly regarding the base memory resources. Even if Windows doesn't report any conflicts, the overlapping of the addresses can cause stuttering sound or other unwanted side effects. In some cases, enabling the memory hole will force a rearrangement of the resources and there is a good chance that this might solve the problems.

IOQ (4 level)

The VIA Apollo chipset family has a four stage pipeline (four buffers) for fast memory reads to the CPU. This pipeline is called In Order Queue or IOQ. The chipset allows for switching between a single buffer and all four buffers, the latter enables buffering a full data burst and, thus, increases the bandwidth quite dramatically. Our own benchmarks show that by enabling IOQ 4 level, system performance is increased by as much as 5% in 3D applications and over 10% in office applications

Read Around Write (enabled)

The memory data path can transmit data only in one direction at a time. This means that a write command will interrupt any reads that are in progress. Writes, on average, only make 5-10% of the entire memory transfer, however, a single bit write can cause a substantial delay in the read memory traffic. To avoid this problem, the memory controller has a read around write (RAW) buffer in which the write data are collected and then written as a burst to memory. In addition, the RAW buffer can act as an additional miniature cache in that the CPU can read directly out of the buffer without accessing the main SDRAM. The RAW buffer (or its equivalent) will become more important for the SMP systems based on the AMD 762 North Bridge in that it will allow snooping or sharing of data between several CPUs without accessing the main memory.

PCI Dynamic Bursting (enabled) sometimes called Byte Merge (enabled)

Instead of transferring single bytes at a time, burst mode uses a packaging transfer protocol to merge individual writes into a single 32 bit block of data (4 words) and transfer them on a single command. A prerequisite for execution of byte merge is that the individual bytes posses a high locality (are coherent data)

PCI-to-DRAM Prefetch (enabled)

In order to avoid repetitive accesses to the system memory for retrieving small pieces of data, an entire area of memory can be prefetched, based on the locality of coherent data. This means that the data are already in the buffer before they are needed and can be accessed with very low latency. This mode can enhance sound card and IEEE 1394 PCI card performance.

CPU-to-PCI write buffer (enabled)

When this feature is enabled, up to four data words can be written to the buffer to be queued to the PCI when it is ready to receive data. If this feature is disabled, the CPU can only write to the PCI bus directly and has to wait for the PCI bus to be ready to receive data. Enabling the buffer can drastically reduce the wait stages (idle cycles) of the CPU.

High Priority PCI mode

When enabled, this setting gives a higher priority to the first PCI slot which can boost performance if a IEEE 1394 PCI card is used.

PCI Master Read Caching

One new setting in the BIOS of the ASUS A7V is the PCI master read caching which supposedly has to be enabled with the Thunderbird and disabled with the Duron. In reality, PCI master read caching does not refer to L2 or L1 in a CPU, but to the ability of the controller to read data ahead of the PCI master from memory into a buffer, especially during burst cycles (memory read line and other advanced commands). Now, if this is cacheable memory, the controller will have to force a snoop to the CPU. (Thanks to ByteEnable for the clarification)

Delayed Transaction / PCI 2.1 support / passive release (only if ISA cards are present)

ISA cards are running at ¼ of the PCI speed, that is 8 1/3 MHz on a 16 bit wide bus. Therefore, the transfer of data to the system bus is slower than the PCI interface and, often, exceeds the PCI latency. If PCI devices try to access the bus while it is occupied by an ISA device, the PCI device can write to an integrated 32 bit buffer within the chipset. The data are temporarily held there and then written to the bus by passive release This setting is only relevant if ISA cards are present in the system

next page:    => more BIOS settings =>