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Virus Warning (Enabled)

In most cases, the first entry in Advanced BIOS features is Virus Warning which can either be enabled or disabled. When enabled, the BIOS performs a Pre-Operating System Check for viruses that could possibly modify the bootsector of the HDD. If any modification or scheduled modification is encountered, the boot process will come to a halt and the DOS prompt will generate the message Boot sector is about to be modified, do you wish to continue? Y / N.

In principle this BIOS-based virus check is very helpful in that it catches boot sector viruses like the infamous NYB virus, and, therefore, should be enabled under normal operating conditions.

However, the same virus protection will also prevent the installation of an operating system since, necessarily, the data are written to the boot sector. Consequently the virus protection will step in and attempt to crash the new installation of the operating system (like Windows). If a new installation of Windows crashes right after the hard drive check, the virus protection is, in most cases, the culprit.

All modern CPUs have at least one level of internal cache memory composed of extremely fast, transistor-based, SRAM (in contrast to the capacitor-based DRAM constituting the main memory). The function of the internal (or, correctly, level 1 or L1) cache is to store data and instructions that have been read from the main memory and are written back to the cache for faster access in case they are requested again. Further, read ahead and storing of prefetched data for write allocation based on the locality of coherent data is performed by the L1 cache

In all cases, this setting should be enabled.

External Cache (Enabled)

Up to the days of the SuperSocket7 platform, the L1 cache was the only internal cache. In most cases, the L1 cache is 32, 64 or 128 kByte which limits the amount of information that can be stored within. As a backup, a secondary, much larger cache was added. In the Socket7 architecture, the secondary or level 2 (L2) cache was added to the mainboard in form of designated, fast cache chips split into data/instruction cache and further the so-called tag RAM.

The data/instruction L2 could vary in size from 512 kB over 1 MB up to 2 MB of on-board cache in the latest versions of the SuperSocket7 boards such as the FIC PA2013 and the Tyan S1598.

The function of the tag RAM was to act like a table of contents for the main memory, that is, to keep the addresses where relevant data were stored within the main memory for faster access. Depending on the width of the tag RAM, the chipset could cache up to 512 MB of system memory, in most cases, however, the limitation was either 64 MB (Intel TX, VX chipset) 128 MB ALi Aladdin V or 256 MB (VIA VP2, MVP3 and MVP4 chipset. In the case of the ALi Aladdin chipset, the situation was a bit more complicated since there was a bug in the original design, causing the need for mainboard manufacturers to add their own tag RAM to the cache. In most cases, the amount of system memory cacheable is evident from a –8 or –10 stamped on the tag RAM chips, standing for 8 bit or 10 bit and corresponding to 128 and 256 MB cacheable system SDRAM, respectively.

The Intel PentiumII was the first CPU to abandon the L2 cache integrated in the mainboard and instead, employing two 256 kB cache chips (total of 512 kB) mounted on the backside of the slot1 PCB which gave this particular type of L2 cache the name backside cache. AMD's Athlon classic followed this example, however, the cache chips were mounted on the front (which didn't change the name of backside cache for the general public, though).

The reasons for this design are quite obvious. Cache chips mounted on the mainboard are prone to variations in trace length or manufacturing tolerances that can have a strong impact on the overall performance of the cache chips. Moreover, since economy drives the manufacturing and marketing process, oftentimes, different versions of the cache chips were used within the same revision of mainboard, causing very different speed characteristics from one board to another. With the backside cache, the question of the cache was entirely in the hands of the CPU manufacturers and, thus, could be custom-tailored to the specific speed grade of a given CPU.

As a Rule of Thumb, the backside cache would run at ½ of the actual CPU clock speed, e.g. in a 300 MHz CPU, the L2 would run at 150 MHz. The highest frequency, though, that can be achieved with a design like this is approximately 350 MHz. In later versions of the Athlon Classic, that is above 700 MHz, the cache divider was changed to 2/5 of the clock speed and, above 900 MHz, to 1/3.

After the debacle of the first Celeron, Intel started to integrate the L2 cache into the CPU core. It was necessary to reduce the cache size to 128 kB in order to fit the additional transistors (6 transistors / bit) in to the die. However, because there was no dead time caused by data delay due to traces away from the CPU, the L2 cache could be run at full speed.

The AMD K6-III followed this example, as did the Coppermine series of Intel CPU and the AMD Thunderbird and Duron. All currently made processors have the L2 cache integrated into the CPU core.

Therefore, the External Cache statement is no longer correct. However, regardless of whether external or internal, it is hard to envision any situation where the L2 cache would need to be disabled. In other words, the setting External cache should always be enabled. There are some boards where loading the Fail-Safe settings disables the External Cache. If the system runs really slow, this is a setting that should be checked.

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