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Memory timing and performance settings

In most cases, the Advanced Chipset Features start out with the DRAM Timing settings. Most manufacturers have carried over this field from the days of fast page and EDO memory which are still supported by some of the VIA chipsets, but cannot be run on any of the modern boards since the higher voltages for EDO are no longer supported by the power supply circuitry, even though some manuals state otherwise. Essentially, in almost all cases the entries use a completely outdated terminology and, further, are either redundant or counterintuitive in that they suggest faster settings where, in fact, the opposite is the case.

Needless to say that there is quite a bit of confusion regarding this field but I'll try to dissect the different settings as well as to give an explanation of their functional significance. Before going into details, it is necessary, however, to give a little background information about the parameters that are contribute to the DRAM timing as a general topic.

SDRAM (same as DDR) is not infinitely fast. DRAM consists of capacitors, gating transistors and bitlines and wordlines (data lines and address lines). Capacitors and lines need to be precharged and the address strobes need time to lock into the correct position in order to retrieve the data.

• 1. The typical cycle starts with a bank activate command that selects and activates one bank and row of memory through the input pins.
• 2. During the next cycle, the data is selected onto the data (or bit) lines and moves towards the sense amplifiers.
• 3. When the data bits reach the sense amplifiers the data is latched by an internal timing signal.
• 4. This process takes length of time called the Row Access Strobe to Column Access Strobe delay (RAS to CAS delay) with a latency of usually two or three cycles.
• 5. After this delay, a read command can be issued along with the column address to select the address of the first word to be read from the sense amplifiers.
• 6. After the read command there is a CAS delay or latency while the data is select from the sense amplifiers and clocked to the output pin. The CAS latency is typically 2 or 3 cycles. Once the data is released to the bus, another word is output every cycle until the data burst is complete.
• 7. Only after all the information has been output, the data can be moved back from the sense amplifiers to the row of cells to restore its contents. Movement of the data back to the empty cells again takes 2 to 3 clock cycles.
• 8. Depending on the leaking or bleeding of the memory cells, the quality of the charge may have to be restored during a so-called refresh cycle. The need for a recharge is determined by a refresh controller whereas the actual process of refreshing is monitored by the refresh counter. This refreshing requires additional 7-10 clock cycles during which the data flow is interrupted and, thus results in a performance hit.

The typical timing settings that decide over performance are:

SDRAM CAS Latency, CAS-DL; often called DRAM cycle time (n cycles): number of cycles the column address strobe needs to select the correct address.

SDRAM tRAS-to-CAS Delay, tRCD; often described as Bank X/Y DRAM timing: (n cycles) number of cycles from when a bank activate command is issued until a read or write command is accepted, that is, before the CAS becomes active. In other words, after a bank activate command, the RAS lines need to be precharged before a read command (specifying the column address) can be issued. This means that the data need to be moved out of the memory cells into the sense amps which takes somewhere between 2 and 3 penalty cycles. It is important to know that tRCD only plays a minor role in the overall penalty since most reads occur as page hits, data are read out of a page already open (but see below). Unfortunately, in most BIOS, tRCD is not directly accessible, at least not under its real name but is hidden in the Bank X/Y DRAM Timing field.

SDRAM SRAS Precharge Delay: tRP (n cycles) necessary to move the data back to the cell of origin (close the bank / page) before the next bank activate command can be issued.

The weigthing of different latencies

Somewhere between 30 and 60% of all read requests fall within the same page (or row) which is called a page hit. In this case, there is no need for the bank activate and tRCD, the data are already in page and the only thing that needs changing is the column address via the Column Address Strobe. Therefore, the CAS-latency becomes the most important factor in the performance of the main memory subsystem.

If the data requested are not found within the same page, the data need to be moved back to the memory cells and the bank will be closed. There are two different cases to be considered.

• Either, the data are located in the same bank but in a different row, in this case, a precharge command needs to be issued, the bank will be closed within two or three cycles (tRP) and a new bank activate command will open the correct row (tRCD). Subsequently, a read command will select the correct column address (CAS delay). In this case, the full number of penalty cycles for CAS-DL, RAS-to-CAS and precharge will pass until the next data are output. In the case of a 2:2:2 DIMM, this will mean 6 penalty cycles, with a 3:3:3 part, the latency will increase to 9 cycles
• If the requested data are located in a different row, it is not necessary to wait for the first bank to close and, thus, tRP can be skipped. Consequently, the latency only comprises tRCD and CAS-DL. Precharging of the first bank (closing the page) can then occur in the background of RAS-to-CAS delay of the second bank.

It does get a bit more complicated than that. If data are contained within the same bank but in a different row, the bank needs to be closed and reactivated. In this case, the bank cycle time SDRAM tRC becomes a critical factor since every bank has a minimum time that it needs to stay open.

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