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| LostCircuits BIOS guide What You Never Wanted To Know But Constantly Dared To Ask | |
| (by MS, Timeless) |
Memory Latencies And Their Hardware Basics
Memory latencies can be varied depending on the performance of the DRAM chips used. CAS, tRCD, tRP, most BIOS settings have means to increase or lower the latency cycles. Typical numbers in SDRAM are 2 and 3. As we know, CAS-2 means that the data will be output on the second rising clock edge after a read command, CAS-3 means that data output happens on the third rising clock edge after the read command.
For CAS latency, the situation is entirely different in that the data, once they are retrieved from the sense amplifiers, are charges that are moving along the data lines towards the output pins and as such, they are very volatile. To extend the life span of the data beyond a single cycle, it is necessary to insert output buffers into the output path. The advantage is that the output buffers are pipeline stages that are in general faster than the sense amplifiers when it comes to releasing the data and furthermore, there is no more address strobe necessary to select the correct column address.
On a functional level, this has the consequence that the access time (tAC) for CAS-1 will always be the sum of the address strobe and the time it takes to spit out the data while the access time for CAS-2 and higher will only be the time required to move the data from their respective pipeline stage to the output pin on the module. Typical examples are in the order of 10 and 3.5 ns for tAC1 and tAC2,3, respectively.
The main problem with the use of intermediate buffers is that the number of pipeline stages inserted into the path will define the number of latency cycles since the data are held within each stage for one clock cycle (in the case of DDR, it can also be 1/2 clock cycle). This implies that it is impossible to run a CAS-2 part at CAS-3. We do know, however, that almost every memory module rated at CAS-2 will be able to run at CAS-3 as well. The technology to enable flexible CAS latencies is the so-called programmable CAS latency, brought to the DRAM world by none other than Rambus Inc.
Programmable CAS latency can be achieved by inserting bypass switches into the output path between the Sense Amplifiers (SA) and the output pins to bypass the pipeline stages P1 and P2. The illustration shows an example of an EMS HSDRAM chip capable of running in CAS-1, -2 or -3 mode. Depending on the mode register set (MRS) command issued by the controller during initialization, the switches (S1 and S2) are left open (CAS-3) to force the data through the buffers, or closed to establish a fast bypass (CAS-1). Alternatively, one single switch can be opened so that the data still have to go through one buffer but can bypass the second for CAS-2 operation.
According to the above, only CAS latencies that are established in form of pipeline stages can be programmed. This in turn means that regardless of whether a BIOS offers e.g. a CL-1.5 setting or a CL-3 setting, those can and will not work if the chips used on the modules only have the pipeline stages for CL2 and 2.5 operations.
Once again, we also see rather often that BIOS settings are specified in the graphics interface but not executed on the PCI register settings. This is exploited by unserious DRAM and module vendors to claim that their modules will, for example, work at CL-1.5 which is nothing but fraud and false advertising.
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