Since at this time, there is no WPCREDIT plugin for the M1647 North Bridge available, I used the ALi datasheet to unravel the different parameters that are changing from one setting to the other. Differences in the settings were highlighted by Photoshop subtraction of screencaptures of WPCREDIT at the different performance settings. One such subtraction is shown below.
The individual Hexcodes were then converted into binary code to look up the register setting for each relevant bit:
The individual hexadecimal values for each offset changed from one DRAM Performance setting to another were entered into an Excel Spread Sheet and converted into binary format. Please consider that each offset consists of 8 bits but Excel does not display numbers starting with 0. Therefore, 101 would correctly read 00000101.
Use the datasheet of the chipset to decode the individual binary bit assignments relating to the respective offset. Despite the simplicity of this approach, with the B- revision of the ALiMAGiK1 chipset, it turned out to be a mammoth task since no less than 12 registers were changed from one DRAM timing setting to the next. Some of the settings were not explained in the datasheet either, others were floating tri-state bits that randomly change upon each reboot, others again were patches for incorrectly functioning registers. Fortunately, with the C revision, things were cleaned up substantially, resulting in only a handful offsets that are changed throughout the different timing settings.
In any case, here are the different parameters as they are assigned by the individual BIOS settings. All settings shown here represent only changes in the DRAM performance field, all other parameters were kept constant:
- CAS latency: 2
- Refresh Queue: 8 Depth
- Enhanced Page Mode Timer: 128 Clk
- Refresh Rate: 15.6 µsec
- CPU / Memory Clock: 133 MHz (266 MHz data rate)
Using the ALi M1647 white papers, it was possible to decode the bit assignment into some meaningful timing parameters.
Why is it necessary to go through these motions? As mentioned in the beginning, there are quite a few more parameters that need to be addressed in the DDR world than just CAS, tRCD and tRP, the common 2:2:2 or 3:3:3 entries. Let's take a look at the individual settings and what they mean:
- R/W Turnaround: the number of wait states after a read until a write command can be issued. Lower numbers result in faster bus-turnaround and, thus, better performance.
- Highway Read: If no operation is scheduled (NOP), the memory command bus is idle-parked, meaning that it goes into standby mode if no consecutive read commands are scheduled. If the idle-park bit is disabled, the memory command bus will be parked on CAS READ, which results in a zero latency on the next read command.
- DDR Read Path Short Latency Mode: This feature applies for DDR only and specifies the time when a read command can be issued (during an ongoing burst).
- tRAS: number of cycles necessary to develop the full charge differential between bit and reference lines to restore the data in the memory cells. Also called the minimum page open time for the reason mentioned.
- tRCD: RAS-To-CAS Delay; bank activate time, the minimum time after a bank activate command until a read command can be issued.
- tRP: RAS Precharge; after a page miss or if a page expires, the RAS lines have to be reset to a neutral state by precharging them before the next bank activate command can be issued.
- tRC: Bank Cycle Time; The sum of tRAS and tRP.
- tDPL: Data Phase Latency; Turnaround between the last Write Data Phase until a precharge command can be issued. Also called tWR or write-to-read interval.
- MWB Write Buffer Timeout Flush: Master Write Buffer Timeout Flush; the MWB has a buffer valid window that can be preset to a certain number of memory cycles, after which it will be flushed. Disabling the force-flushing can increase performance but also bears the inherent risk of data corruption.
There are some other parameters that can be set individually:
- PLT Enable: The M1647 memory controller offers the possibility to close all pages if the Page Life-Time counter expires
- PLT: Page Life-Time: (Enhance Page Mode Time) ; One of the fundamental differences between the M1647 memory controller and the controller as implemented in the AMD 761 North Bridge is the way of how the page expiration is controlled. The AMD 761 controller has a so-called Page Hit Limit (PH Limit), which limits the number of consecutive page hits and forces a page to be closed before it expires. The ALi M1647 controller does not measure page hits but relies on bus cycles to determine the expiration of a page. However, this timer only becomes active after the bus is idle since each read / write command resets the counter. As a consequence, as long as consecutive R/W commands are issued, the page stays open until a miss occurs.
- DRAM Refresh Queue (1-8 Level)
DRAM needs to be refreshed at a certain interval and this can be done one row at a time or in a queued manner in which a certain number of rows are refreshed in burst mode. Depending on which level is specified, up to 8 rows (pages are refreshed sequentially).
For more detailed descriptions of these parameters please check the main index of this article
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