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SiSoft Sandra Memory Benchmark

At the default setting, that is Normal, CAS-2.5, Command Rate 2T and no bank interleaving, the memory benchmark turned up rather disappointing numbers, which is not further surprising. Reducing the command rate to 1T by switching to the Fast setting increased the bandwidth substantially, a further increase was achieved by reducing tRCD, tRP and tRAS latencies by moving to the Fastest setting.

A much greater performance increase was achieved by enabling 4 bank interleaving, whereas changing the CAS latency to from 2.5 to 2 had very little effect. One setting that has absolutely no effect is to reduce tRAS to 5 cycles which is predictable since this setting is not supposed to have any bearing on performance. However, running tRAS at 5T instead of 6T does have some severe impact on stability and can lead to data corruption that is not even apparent until the next reboot and further can lead to hard drive failure.

SiSoft Sandra memory benchmark scores. Except for the top two results, all runs were performed at 133 MHz bus speed. The different runs start (bottom to top) with Normal, Fast, Fastest, no interleaving and CAS 2.5. The next higher set of data are Normal, Fast Fastest with 4 bank interleaving enabled, the "/6" indicates where the Active to Command latency (tRAS) was increased from 5T to 6T. Above that, the same sequence but with CAS-2 and tRAS always at 6T. The top two data are results of running at 160 MHz bus speed at the Normal and the Fastest setting (tRAS forced to 6T). What is very clear here is that changing tRAS from 5 to 6 does not change the performance. However setting tRAS too short can lead to data corruption and hard drive failure.

Bottom line is that with DIMMs that may not be top grade, the performance can still be tweaked to quite respectful scores by e.g. running the system at Normal, 4 bank interleave with either CAS-2 or CAS-2.5

Expendable

Usually, Expendable Timedemo follows the patterns of SiSoft Sandra rather closely. There is, however, one major difference in that CAS latency becomes a more prominent factor regarding the performance. Naturally, CAS latency will matter more at lower performance settings since at the fastest settings other limiting factors will mask the effect of lower CAS latency. Once again, changing tRAS from 5 to 6 cycles has zero effect on the benchmark scores.

Average fps of Expendable Timedemo at 640x 480 x 16bpp. The trend is quite similar to SiSoft Sandra but CAS latency has a much greater impact. Again, note that changing tRAS to 6 has no impact whatsoever on the performance. Once again, take a look at the Normal setting with 4 bank interleave and CAS-2 which is probably the highest performance at the lowest stress setting.

KT333 and KT400 and latencies

Both chipsets support DDR333 or PC2700 as well as a 333MHz CPU bus interface. The KT400 further supports DDR400, however, there is no benefit at all to run the memory at the higher speed since it requires to de-synchronize the processor and memory bus. This, in turn makes it necessary to add fifos and synchronizers into the memory path both of which increase latencies, particularly the initial access latency or tRAC. On average, these additional latencies result in a 1-5% performance degradation, even if the memory is running in DDR400 mode at 2:2:2 latencies. If the recommended latencies of 2.5:4:4 are used, the performance hit compared to DDR333 gets even worse.

On the mainboard level, the KT400 has reinstated the dark ages of sloppyness with respect to BIOS settings that are listed as opposed to what is really supported by the chipset. One of the key issues that is seen over and over again is the listings of tRCD and tRP values of 3T in DDR 400 mode. Plain and simply, the chipset does not support these latencies meaning that in DDR400 mode the only valid values are 2T and 4T. Unfortunately, the mislabeling is also being exploited by memory vendors that are using the fake BIOS settings to claim lower latencies for their modules, that is 2:3:3 latencies in DDR400 mode.

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