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| LostCircuits BIOS guide What You Never Wanted To Know But Constantly Dared To Ask | |
| (by MS, Timeless) |
Back to real life situations
In most Award BIOS setups of VIA chipset boards, the memory timing fields have been carried over from the fast page and EDO times and, thus, use terminology that has little or nothing to do with the current state of memory technology. In addition, it is not a single parameter that is changed by selecting one entry over the other, rather it is an entire cocktail of setting that is modified.
Bank X/Y DRAM Timing (Mixture of tRC + tRCD + bank interleaving)
The standard settings are:
| Setting | tRAS | tRP | CAS | DDR-WE | tRCD | interleave |
| SDRAM 8-10ns | 6T | 3T | n/a | disabled | 3T | 0 |
| Normal | 5T | 2T | n/a | disabled | T | 4 way |
| Medium | 6T | 3T | n/a | disabled | 3T | 0 |
| Fast | 6T | 3T | n/a | disabled | 3T | 0 |
| Turbo | 6T | 3T | n/a | disabled | 2T | 0 |
It is important that there is no difference between 8-10 ns, Medium and Fast, all of which give relatively low performance values. Selecting Turbo reduces tRCD to 2T which can cause compatibility problems with EMS HSDRAM 150.
More importantly, 4-way bank interleaving, another performance enhancing measure is natively enabled by the Normal setting which, further, reduces tRAS to 5 cycles while maintaining a total bank cycle time of 8T.
In terms of performance, it is obvious that there are no differences between the 8-10ns, medium and fast setting, but here are some surprising results:
SiSoft Sandra memory benchmark results depending on the DRAM timing setting in the BIOS alone. The test system in this case was a Shuttle AV14 mainboard, running at 112 MHz x 6, with the memory running at host clock. 1 x 128 MB HSDRAM.
Interestingly, setting tRCD to 2T while enabling 4-way interleaving was found to cause some stability problems which may be the reason that this combination is not usually supported by the BIOS.
The settings reported here are typical for most VIA chipset boards, built around the VIA 691A, 694X , the KX 133 and the KT133 North Bridge and were found to be identical across all boards tested, based on the bit assignment in the respective chipset registers. This, however, does not mean that there aren't any exceptions caused by manufacturers who either have the know-how and label the settings correctly (like ASUS) or try to tweak their boards using the existing entries to mean different values from those described here.
CAS-Delay (CAS latency, in most VIA chipset BIOS falsely described as DRAM cycle time)
In most BIOS, CAS latency has its own separate entry and, the lower the latency is, the better will be the performance. CAS latency is the most important performance parameter in the memory subsystem for the reasons outlined above.
next page: => more BIOS settings =>
