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SPD (Serial Presence Detect)

In order to standardize the SDRAM interface, the so-called Serial Presence Detect was introduced in 1998 as part of the PC100 specifications hammered out by Intel. The SPD is a small EEPROM located in the corner of the DIMM's PCB and contains all necessary specifications of the DIMMs including speed of the individual components as CAS and bank cycle time as well as valid settings for the module and the manufacturer's code. In addition, parameters like the width (64 bit for standard, 72 bit for ECC) are stored in the SPD chip. The SPD enables the BIOS to read the spec sheet of the DIMMs on boot-up and then adjust the memory timing parameters accordingly.

One potential drawback of the SPD is that it is not write protected and, thus, anyone with an EEPROM writer can reprogram it to show data out of specs which suggest better quality than actually present. These are just a few reasons not to trust the SPD entirely and, rather, use the manual settings as outlined above.

DRAM clock

Intel BX / AMD 751 Irongate

In the case of the Intel BX443 and the AMD 751 Irongate Northbridge, the memory bus is always running synchronous with the front side bus (FSB, system bus). That is, the memory bus will always run at the exact frequency of the system bus, meaning, that overclocking the system bus will also overclock the memory bus.

VIA chipset family

The VIA Apollo 133 chipset allows to run the memory at harmonic frequencies of the CPU bus (FSB), that is, the PCI frequency can be added or subtracted from the CPU bus. Bit 6 and 7 at offset 69 in the VIA chipset register specify the memory bus frequency. In theory, there are three settings, namely:

• memory at host clock (FSB),
• memory at host clock - 33 MHz.
• memory at host clock + 33 MHz

In real life, the situation is more restricted than that, in that running at the 133 MHz FSB precludes activation of the +PCI setting, just as running at 66 MHz FSB precludes the - PCI setting. In other words, here are the valid options:

Please keep in mind that the memory bus follows the CPU bus under overclocking conditions with a proportional increase / decrease in frequency. This means that a 110 FSB + 33 (in reality PCI freq.) will result in 146 MHz and not 143 MHz. Likewise, at 120 MHz FSB, the memory bus will hit 160 MHz.

Intel i815(E) chipset

The i815 chipset differs from the VIA chipset family in that it doesn't allow to run the memory faster than the CPU bus, with the exception of the 66 MHz setting which defaults to the 100 MHz memory bus. At 100 MHz, the memory bus is locked at 100 MHz as well. At 133 MHz FSB, the memory can run in 4:3 (FSB:memory bus) ratio as well as at 133 MHz (1:1 ratio).

i815 Bank limitiation and its impact on the memory bus frequency

In order to prevent memory failure at higher bus speed and increased memory load, Intel has added a bank sensor to their memory slots, signaling to the chipset if more than 2 DIMM slots (4 banks) are occupied. If this is the case (three DIMMs), the chipset automatically defaults back to the 4:3 mode, meaning that even at the 133 MHz FSB, the memory bus will run at 100 MHz only.

Intel i850 chipset

RDRAM Frequency selection in the ASUS P4T

There are three settings, Auto, 3:1 and 4:1. The "Auto" setting actually runs the RIMMs at their designated speed ratio. RIMMs are, unfortunately, though, not too stable when overclocked. The P4T offers the workaround by allowing to run PC800 RIMMs as PC600 RIMMs by specifying the 3:1 setting in the BIOS. This way, the FSB can be overclocked beyond the limitations of the memory bus (provided that PC 800 RIMMs are used, more below).

DRAM read latch delay (VIA chipset only)

If the memory clock frequency is increased, the cycle time gets shorter. Therefore, the data valid window (tDV), that is the time during which the chipset can receive data from the DRAM would come earlier (on an absolute time scale) and could possibly expire before the data from the DIMMs arrive. In order to compensate, tDV needs to be delayed or moved further back on the cycle to synchronize with the data output holding time of the DIMMs. In the case of the KT chipset, the situation is a bit more complicated since the Athlon family uses what is called clock forwarding or clock syncronous transfer. That is, a reference signal synchronizes all devices. Keep in mind that the KT chipset is a variation of the KX chipset and based on the timing parameters of the original SlotA Athlon. The socketed Thunderbird has shorter traces and, therefore, is able to receive data earlier relative to the originally established timing characteristics. Therefore, for example, the ASUS A7V BIOS even features a negative DRAM read latch delay of 0.1ns, that is, the data valid window opens even before the reference signal arrives. With all DIMMs tested, though, the Auto setting worked as well as any other manual setting.

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