LOSTCIRCUITS	SHORTCUTS: LDT & PCI Bus Control / HT Link Control HT Multiplier Configuration HT Width DRAM Configuration Timing Mode (Auto) / SLI-Ready Memory Memclock Index Value (MHz) (200 MHz) Changing the CPU Multiplier Invalidates SLI Memory Performance Options Odd Divisor Correct CAS# latency (tCL) Min RAS# to Active time (tRAS) RAS# to CAS# Delay (tRCD) Row Precharge Latency (tRP) Row-to-Row Delay (tRRP) Row Cycle Time (tRC) Row Refresh Cycle Time (tRFC; tREF) Read to Write Time (tRWT) Refresh Rate Write Recovery Time (tWR) 1T/2T Memory Timing / Command Per Clock (CMD) Read Preamble Value Async. Latency Value)	Async. Latency Value) Dynamic Idle Cycle Counter IdleCycle Limit Read/Write Queue Bypass / Bypass Max Drive Strength Settings DQS Hysteresis Digital Locked Loop (DLL) Read DQS Skew Read Delay from Rx FIFO DQS Training Control DRAM Bank Interleaving Burst Length (4 beats-8 beats) / 32Byte-64Byte Granularity MTRR Mapping Mode DRAM Voltage VDIMM DRAM VTT Offset DRAM On-Die-Termination CPU VID Control CPU FID Control PCIe clock Bus and Chipset Voltages (RADEON XPRESS Chipsets) Legacy Settings Miscellaneous Comment on This Article
BIOS Settings for the Athlon 64 Platform     including AM2
(MS, June 19, 2006)

The recent introduction of AMD's AM2 platform has added a plethora of new BIOS settings above those that were available so far. Rather than adding those settings to our BIOS guide where they would probably get buried under legacy descriptions of settings that are almost obsolete, we decided to start from scratch with a new set of explanations for all settings that we could find and that are of relevance or at least interest to the overclocking community as well as to the technically versed that just wants to be put in the know.

Also, for some of the settings, we have taken a somewhat different approach in that we describe the actual hardware first and then tie it into the functional consequences of the settings. Beware, we tried to make it as easy as possible but at times it may still get a bit technical.

Every motherboard manufacturer, chipset manufacturer or BIOS provider has their own "proprietary" parlance, some of it may be just reluctance to adjust to the current nomenclature, some is for bragging rights but whatever it is, BIOS descriptions are approaching confusion of Babylonian dimensions. In this article we are therefore showing any term of describing a particular setting that we have come across in the different motherboards and manuals that were the basis for this article.

There is no need to try and understand every single part of this article at first read but hopefully this will take out some of the myth surrounding some of the settings and further help finding the correct parameters for a given system according to some of the example values shown. And sorry, we don't have pretty pictures here....

LDT & PCI Bus Control / HT Link Control

The internal code name for the bus protocol now known as HyperTransport (HT) used to be Lightning Data Transport or LDT. Even several years after abandoning it, the original code name is still floating around - an example of how difficult it can be to get rid of historic baggage. HyperTransport constitutes a highly scalable bus interface running in full duplex mode, which means that the link is divided into two separate buses: one for upstream and one for downstream data transfer (to and from the CPU, respectively). Each bit uses a low voltage differential signaling (LVDS) pair of two complementary data lines with mirror-symmetric signals that are compared against each other. Under the HT 2.0 umbrella, each HT signaling pair provides 2000 Mbit/sec data bandwidth using a DDR protocol on a 1000 MHz clock rate. Therefore, a 16 bit interface will support as much as 4 GB/sec data bandwidth in each direction. Since concurrent upstream and downstream data transports are supported, the theoretical maximum concurrent bandwidth is 8 MB/sec.

The maximum HT interface width supported by current AMD processors is 16 bit wide in each direction, however, the interface is scalable and allows selective disabling of eight of the 16 data lines in each direction. For optimal performance, all 16 lanes in both upstream and downstream signal pathways should be enabled.

One major difference between for example ATI's RADEON XPress crossfire chipsets and the nVidia nForce5 chipset is that the Crossfire platform connects the North Bridge with the South Bridge through the PCIe interface, whereas the nForce5 chipset uses the secondary HyperTransport link for the connection between the SPP and the Media and Communication Processor (MCP)

The HT interface 2.0 is specified for optimal signal characteristics when running at 1000 MHz, in other words, the trace layout is optimized for a 1 GHz clock rate. Any frequency below or especially above the nominal value will generate resonance to a certain extent or signal reflexions known as ringing. It is, therefore, highly advisable to keep the HT frequency as close as possible to 1000 MHz. The actual HyperTransport frequency is derived from the external bus input clock and the multiplier. Typical AMD-based motherboards run the external input clock at 200 MHz with a multiplier of 5 x, resulting in a clock rate of 1000 MHz. If the external clock is overclocked, the ratio of the HT bus multiplier needs to be lowered to bring the resulting HT frequency back to 1000 MHz.

HT Multiplier Configuration

The nForce5 chipset allows fine-tuning of essentially every single component of the HyperTransport subsystem, for example the HT multipliers can be set separately for the CPU to nForce SPP HT link (simultaneously for upstream and downstream), and also for the secondary HT-link between the nForce SPP and the nForce MCP, in which case the upstream and downstream links can be configured individually in the following tabs:

• nForce SPP => nForce MCP
• nForce SPP <= nForce MCP

Likewise, both HT-links can be configured separately as to their width, that is 16 bit or 8 bit wide:

HT Width

• CPU <= => nForce SPP
• NForce SPP <= => nForce MCP

Finally, the nForce5 chipset allows configuration of the SPP to MCP HT reference clock separately from the CPU to SPP reference clock

• SPP <= => MCP Ref Clock

next page:    => DRAM Configuration =>

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