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LOSTCIRCUITS	SHORTCUTS: LDT & PCI Bus Control / HT Link Control HT Multiplier Configuration HT Width DRAM Configuration Timing Mode (Auto) / SLI-Ready Memory Memclock Index Value (MHz) (200 MHz) Changing the CPU Multiplier Invalidates SLI Memory Performance Options Odd Divisor Correct CAS# latency (tCL) Min RAS# to Active time (tRAS) RAS# to CAS# Delay (tRCD) Row Precharge Latency (tRP) Row-to-Row Delay (tRRP) Row Cycle Time (tRC) Row Refresh Cycle Time (tRFC; tREF) Read to Write Time (tRWT) Refresh Rate Write Recovery Time (tWR) 1T/2T Memory Timing / Command Per Clock (CMD) Read Preamble Value Async. Latency Value)	Async. Latency Value) Dynamic Idle Cycle Counter IdleCycle Limit Read/Write Queue Bypass / Bypass Max Drive Strength Settings DQS Hysteresis Digital Locked Loop (DLL) Read DQS Skew Read Delay from Rx FIFO DQS Training Control DRAM Bank Interleaving Burst Length (4 beats-8 beats) / 32Byte-64Byte Granularity MTRR Mapping Mode DRAM Voltage VDIMM DRAM VTT Offset DRAM On-Die-Termination CPU VID Control CPU FID Control PCIe clock Bus and Chipset Voltages (RADEON XPRESS Chipsets) Legacy Settings Miscellaneous Comment on This Article
BIOS Settings for the Athlon 64 Platform     including AM2
(MS, June 19, 2006)

This field allows for the manual specification of the DDR supply voltage. DDR2 is specified to operate a 1.8V (VDD and VDDQ), however, in the case of high speed memory modules (DDR2 800 or PC6400 DDR2 and higher) it is often necessary to increase the voltage to 2.0 or even 2.1 V.

DRAM VTT Offset (0%)

The termination voltage and reference voltage of DRAM specify the crossover point above or below which a signal is read as either I or O and also the voltage against which the data lines are terminated. In most DRAM devices, therefore, the VTT level is specified as midpoint between the supply voltage (VDD) and ground (0V). Some DRAM devices, however, have asymmetries in their voltage swing, meaning that they reach the high voltage level faster or slower than the low voltage level. In this case, a small performance increase can be achieved by raising or lowering the cross-over point by a certain percentage. Most memory modules will perform best at the nominal value.

DRAM On-Die-Termination

Many memory chips have at least two settings for the resistor value of the On-Die Termination. Typical values are 60/120 Ohm options. On-Die-Termination is turned On in all memory devices that are not active (selected by Chip Select). Termination also causes a current drain to the termination voltage (VTT - see above). With increasing amounts of system memory, the amount of passive current drain through ODT increases, which can dilute the data signals beyond the point of noise cancellation and excessive power consumption with the associated heat dissiation. This problem can be ameliorated by increasing the resistance of each ODT resistor path to the higher value.

CPU VID Control (Startup)

Each CPU has a factory defined Voltage ID (VID) that is read on startup of the system. This field allows the user to manually override the VID and specify a voltage setting from the range of available options.

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