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LOSTCIRCUITS	SHORTCUTS: LDT & PCI Bus Control / HT Link Control HT Multiplier Configuration HT Width DRAM Configuration Timing Mode (Auto) / SLI-Ready Memory Memclock Index Value (MHz) (200 MHz) Changing the CPU Multiplier Invalidates SLI Memory Performance Options Odd Divisor Correct CAS# latency (tCL) Min RAS# to Active time (tRAS) RAS# to CAS# Delay (tRCD) Row Precharge Latency (tRP) Row-to-Row Delay (tRRP) Row Cycle Time (tRC) Row Refresh Cycle Time (tRFC; tREF) Read to Write Time (tRWT) Refresh Rate Write Recovery Time (tWR) 1T/2T Memory Timing / Command Per Clock (CMD) Read Preamble Value Async. Latency Value)	Async. Latency Value) Dynamic Idle Cycle Counter IdleCycle Limit Read/Write Queue Bypass / Bypass Max Drive Strength Settings DQS Hysteresis Digital Locked Loop (DLL) Read DQS Skew Read Delay from Rx FIFO DQS Training Control DRAM Bank Interleaving Burst Length (4 beats-8 beats) / 32Byte-64Byte Granularity MTRR Mapping Mode DRAM Voltage VDIMM DRAM VTT Offset DRAM On-Die-Termination CPU VID Control CPU FID Control PCIe clock Bus and Chipset Voltages (RADEON XPRESS Chipsets) Legacy Settings Miscellaneous Comment on This Article
BIOS Settings for the Athlon 64 Platform     including AM2
(MS, June 19, 2006)

Radeon Xpress 200 Voltage (1.22 V)

Increasing the voltage may allow to reach higher bus frequencies but will also result in higher thermal dissipation of the NorthBridge. In turn, this can mitigate the improvements achieved by the voltage increase.

HT Link Voltage (1.22V)

The HyperTransport link uses a supply voltage of 1.22 V. Increasing the voltage above the nominal value may help with overclocking, However, in the majority of cases, this setting should be left at default.

PCIe 1.2 Voltage (1.22V)

The supply voltage of the PCIe bus is nominally 1.22 V but can be increased in this field for better stability with overclocking. Tip: If either one of the above three voltages is increased, the other two values should be adjusted accordingly to avoid reverse current draw from one to the other bus through the bridge chip.

NB HT PLL Control This field specifies how long it will take for the slowest HT clock Phase Lock Loop to ramp up speed to the new frequency and lock in on this frequency. Since the HT PLLs are transparent to the user, this setting should be left at "Auto" which allows locking in on new frequencies of the variable current oscillators (clock generators). This field is relevant especially for dynamic overclocking where changes in the base frequency are incurred. - PLL High Speed mode (Low Speed) - PLL Stability Calibration (00)

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