Navigate: Advice Beginners BIOS Guide CPUs Links Mainboards Memory Network Storage Video/Sound Cards Contact Forum SiteMap Sponsors Home PC Hardware from Made-in-China.com Search: Enter your search terms   Web www.lostcircuits.com Submit search form	.
Prices:

LOSTCIRCUITS	SHORTCUTS: LDT & PCI Bus Control / HT Link Control HT Multiplier Configuration HT Width DRAM Configuration Timing Mode (Auto) / SLI-Ready Memory Memclock Index Value (MHz) (200 MHz) Changing the CPU Multiplier Invalidates SLI Memory Performance Options Odd Divisor Correct CAS# latency (tCL) Min RAS# to Active time (tRAS) RAS# to CAS# Delay (tRCD) Row Precharge Latency (tRP) Row-to-Row Delay (tRRP) Row Cycle Time (tRC) Row Refresh Cycle Time (tRFC; tREF) Read to Write Time (tRWT) Refresh Rate Write Recovery Time (tWR) 1T/2T Memory Timing / Command Per Clock (CMD) Read Preamble Value Async. Latency Value)	Async. Latency Value) Dynamic Idle Cycle Counter IdleCycle Limit Read/Write Queue Bypass / Bypass Max Drive Strength Settings DQS Hysteresis Digital Locked Loop (DLL) Read DQS Skew Read Delay from Rx FIFO DQS Training Control DRAM Bank Interleaving Burst Length (4 beats-8 beats) / 32Byte-64Byte Granularity MTRR Mapping Mode DRAM Voltage VDIMM DRAM VTT Offset DRAM On-Die-Termination CPU VID Control CPU FID Control PCIe clock Bus and Chipset Voltages (RADEON XPRESS Chipsets) Legacy Settings Miscellaneous Comment on This Article
BIOS Settings for the Athlon 64 Platform     including AM2
(MS, June 19, 2006)

ESCD stands for Extended System Configuration Data and describes a feature that has been implemented with the PnP specifications. The ESCD are stored in a dedicated part of the CMOS memory also referred to as ESCD Pool. The ESCD contain information about the system configuration at the last time the system was booted, keeping a record of the peripheral device configuration that was negotiated with the system and resulting in a conflict-free setup. Keeping a record of these data eliminates the need for re-negotiation of resource allocation and, consequently, helps to speed up the boot time, unless changes in the hardware have occurred. A typical sign for the use of ESCD is the display of an "updating ESCD Pool" string during boot-up.

PCI Latency Timer (CLK) (64)

The peripheral component interconnect (PCI) bus is shared between all interrupts. In order to get access to the bus, each device needs to arbitrate and to capture the bus, which excludes other devices from using it at the same time. Different Interrupt Request lines that are assigned to the individual devices have different priorities which can lead to starvation of a lower priority device by a higher priority device. In order to avoid this problem, fairness algorithms have been implemented to define, for example, how long any device can occupy the bus before it has to relinquish it and check whether there are other system requests that need to be serviced. This interval is called the PCI latency.

Each PCI bus access also needs a certain number of cycles, usually around eight, for the arbitration, including the setup of the device on the bus. The number of setup cycles is fairly constant, irrespective of the total latency. Therefore, a higher number of cycles assigned to the PCI latency will only increase the number of transfer cycles and directly translate into better device performance. On the other hand, with more PCI devices in the system, more devices will vie for the bus and, therefore, very high latencies could result in the above mentioned starvation of one or the other device.

In most modern systems, the empirically found best performance across the board is between 64 and 96 cycles, depending on the feature set that is implemented in the PCI configuration. For example, it is possible to run at lower latencies if so-called bus parking is implemented, that is, the PCI device relinquishes the bus according to the prespecified latency but remains in a “parked” position to facilitate an immediate re-assertation if there is no competition from other devices.

Note that the PCI express (PCIe) bus is not shared with the PCI bus. PCIe interfaces are using dedicated lanes for interconnect that are not shared.

next page:    => Miscellaneous: Power Savings, Memtest =>

All advice and educational articles on LostCircuits are free, but if you feel you can, please make a small donation to us!
Thank you!

---

General disclaimer: This page only reflects the author's personal opinion and assumes no responsibility whatsoever regarding any of the contents or any damages that may occur explicitly or implicitly from reading the contents of this site. All names and trademarks mentioned in this review are the exclusive property of the respective parent companies.
All contents of this site are protected by international copyright laws. Reproduction of the contents even in parts is not allowed except after written permission by the author and referral to this site.
Copyright 2002 - 2008 LostCircuits