Navigate: Advice Beginners BIOS Guide CPUs Links Mainboards Memory Network Storage Video/Sound Cards Contact Forum SiteMap Sponsors Home PC Hardware from Made-in-China.com Search: Enter your search terms   Web www.lostcircuits.com Submit search form	.
Prices:

LOSTCIRCUITS	SHORTCUTS: LDT & PCI Bus Control / HT Link Control HT Multiplier Configuration HT Width DRAM Configuration Timing Mode (Auto) / SLI-Ready Memory Memclock Index Value (MHz) (200 MHz) Changing the CPU Multiplier Invalidates SLI Memory Performance Options Odd Divisor Correct CAS# latency (tCL) Min RAS# to Active time (tRAS) RAS# to CAS# Delay (tRCD) Row Precharge Latency (tRP) Row-to-Row Delay (tRRP) Row Cycle Time (tRC) Row Refresh Cycle Time (tRFC; tREF) Read to Write Time (tRWT) Refresh Rate Write Recovery Time (tWR) 1T/2T Memory Timing / Command Per Clock (CMD) Read Preamble Value Async. Latency Value)	Async. Latency Value) Dynamic Idle Cycle Counter IdleCycle Limit Read/Write Queue Bypass / Bypass Max Drive Strength Settings DQS Hysteresis Digital Locked Loop (DLL) Read DQS Skew Read Delay from Rx FIFO DQS Training Control DRAM Bank Interleaving Burst Length (4 beats-8 beats) / 32Byte-64Byte Granularity MTRR Mapping Mode DRAM Voltage VDIMM DRAM VTT Offset DRAM On-Die-Termination CPU VID Control CPU FID Control PCIe clock Bus and Chipset Voltages (RADEON XPRESS Chipsets) Legacy Settings Miscellaneous Comment on This Article
BIOS Settings for the Athlon 64 Platform     including AM2
(MS, June 19, 2006)

NVMEM Memory Test

Several motherboard manufacturers, particularly DFI have started to inmplement MemTest86 on their boards. Usually, the memory test is started by default on every power up unless it is disabled in the CMOS setup. The nForce5 reference design provides for a similar memory test dubbed NVMEM Memory test. Keep in mind that this is different from what was mislabeled in the past as NVRAM test.

CKE-Base Power Down Mode

All synchronous memory devices can go into sleep mode as soon as the CKE (clock enable) signal is disasserted. In that case, the internal clocks are disabled and the memory chip goes into auto-refresh mode which is the lowest power state at which the memory retains data. If then power is turned off, the device will lose all data, however, as long as standby power is maintained, no data loss will occur. The CKE-based Power Down mode can be enabled or disabled.

CKE Power down control

Power saving through disasserting Clock Enable can be done on a system level or else on a per channel basis. Per Channel is the recommended setting for non-mobile systems

Disclaimer

We cannot guaranty the accuracy of every single line item described here for the simple reason that it is at the discretion of the individual motherboard manufacturers how they label their entries. In the past, we have encountered mislabeled entries more often than we thought possible and that by itself negates any efforts we have made towards accuracy. In addition, some of the descriptions we based our assessment on were more than just a little bit ambiguous, which causes additional vagaries. Overall we are confident that the vast majority of the descriptions is complete and accurate but we won't be responsible for any failed system or computer science exam,

next page:    => More =>

All advice and educational articles on LostCircuits are free, but if you feel you can, please make a small donation to us!
Thank you!

---

General disclaimer: This page only reflects the author's personal opinion and assumes no responsibility whatsoever regarding any of the contents or any damages that may occur explicitly or implicitly from reading the contents of this site. All names and trademarks mentioned in this review are the exclusive property of the respective parent companies.
All contents of this site are protected by international copyright laws. Reproduction of the contents even in parts is not allowed except after written permission by the author and referral to this site.
Copyright 2002 - 2008 LostCircuits