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LOSTCIRCUITS	SHORTCUTS: LDT & PCI Bus Control / HT Link Control HT Multiplier Configuration HT Width DRAM Configuration Timing Mode (Auto) / SLI-Ready Memory Memclock Index Value (MHz) (200 MHz) Changing the CPU Multiplier Invalidates SLI Memory Performance Options Odd Divisor Correct CAS# latency (tCL) Min RAS# to Active time (tRAS) RAS# to CAS# Delay (tRCD) Row Precharge Latency (tRP) Row-to-Row Delay (tRRP) Row Cycle Time (tRC) Row Refresh Cycle Time (tRFC; tREF) Read to Write Time (tRWT) Refresh Rate Write Recovery Time (tWR) 1T/2T Memory Timing / Command Per Clock (CMD) Read Preamble Value Async. Latency Value)	Async. Latency Value) Dynamic Idle Cycle Counter IdleCycle Limit Read/Write Queue Bypass / Bypass Max Drive Strength Settings DQS Hysteresis Digital Locked Loop (DLL) Read DQS Skew Read Delay from Rx FIFO DQS Training Control DRAM Bank Interleaving Burst Length (4 beats-8 beats) / 32Byte-64Byte Granularity MTRR Mapping Mode DRAM Voltage VDIMM DRAM VTT Offset DRAM On-Die-Termination CPU VID Control CPU FID Control PCIe clock Bus and Chipset Voltages (RADEON XPRESS Chipsets) Legacy Settings Miscellaneous Comment on This Article
BIOS Settings for the Athlon 64 Platform     including AM2
(MS, June 19, 2006)

Timing Mode (Auto) / SLI-Ready Memory

In Auto mode, the system reads the electronic data sheet of the memory modules as provided within the serial presence detect (SPD) read only memory (ROM) on each module and adjusts the timings accordingly. One interesting approach in this context is the Enhanced Performance Profile initiative heralded by nVidia that can be enabled via the SLI-Ready Memory tab in nForce5 chipset-based systems. A prerequisite for the EPP functionality is that the memory is "SLI-ready", which means that the SPD needs to feature the additional performance profile entries. Keep in mind that the EPP setting entries in the SPD are not sanctioned by JEDEC but a private initiative between nVidia and several memory manufacturers.

Most overclockers will prefer the Manual settings that allow manual configuration of the following parameters.

Memclock Index Value (MHz) (200 MHz)

This tab allows the user to manually specify the memory clock frequency independent of the system bus frequency. In current AMD systems, the memory clock is derived from the CPU clock. That is, the CPU core clock is divided to generate the desired memory bus frequency. For example, a 2000 MHz clock speed and a /10 divisor will generate a 200 MHz memory clock, whereas a /8 divider will result in a 250 MHz memory clock frequency. The main difference to older designs is that there is no more direct correlation between the external bus (in this case the HT-Link) and the memory frequency, rather it is the overall CPU core speed that defines the memory frequency. As a result, the memory frequencies will vary from one speed grade of processor to another especially when the system or the memory is overclocked. Likewise, if the CPU multiplier is changed, it will impact the memory frequency, which is in contrast to any legacy architecture with a dedicated memory controller as part of the NorthBridge.

This is an important issue to keep in mind when testing memory at different overclocking frequency settings using different CPU multipliers since the actual memory frequency will change even if the settings are kept without changes. In other words, if the memory does work at one given multiplier and a given frequency but not at the same frequency and latency settings if a different multiplier is selected, then that may be caused by the simple fact that the real frequency is different. Likewise, the memory performance will change depending on the multiplier used.

Changing the CPU Multiplier Invalidates SLI Memory Performance Options

The dependency of the memory frequency on the CPU clockspeed and - by extension - on the CPU multiplier is also the reason why changing the CPU Multiplier invalidates the Enhanced Performance Profile in SLI Memory.

Odd Divisor Correct

If enabled, the memory controller eliminates odd divisors from being used for the memory clock. Since the memory clock is derived from the CPU clock by applying a divisor, it is easy to see how the elimination of the odd divisors will impact the overall memory frequency. For example, a CPU running at 2800 MHz and a 1/14 divisor will have a memory frequency of 200 MHz. If the CPU Multiplier is set to 13 for 2600 MHz, and the odd divisors are disallowed, the memory frequency can only be 2600 MHz/12 (216 MHz) or 2600MHz /14 (185 MHz) but not 200 MHz. Bottomline is that the Odd Divisor Correct setting should be disabled for most users. On the other hand, leaving the correction enabled will allow a forced underclocking of the memory even if the frequency settings are not given in the BIOS.

CPU Multiplier

The CPU multiplier can be changed in the CPU Multiplier tab.

next page:    => CAS# Delay (tCL) and RAS Pulse Width (tRAS) =>

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