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LOSTCIRCUITS	SHORTCUTS: LDT & PCI Bus Control / HT Link Control HT Multiplier Configuration HT Width DRAM Configuration Timing Mode (Auto) / SLI-Ready Memory Memclock Index Value (MHz) (200 MHz) Changing the CPU Multiplier Invalidates SLI Memory Performance Options Odd Divisor Correct CAS# latency (tCL) Min RAS# to Active time (tRAS) RAS# to CAS# Delay (tRCD) Row Precharge Latency (tRP) Row-to-Row Delay (tRRP) Row Cycle Time (tRC) Row Refresh Cycle Time (tRFC; tREF) Read to Write Time (tRWT) Refresh Rate Write Recovery Time (tWR) 1T/2T Memory Timing / Command Per Clock (CMD) Read Preamble Value Async. Latency Value)	Async. Latency Value) Dynamic Idle Cycle Counter IdleCycle Limit Read/Write Queue Bypass / Bypass Max Drive Strength Settings DQS Hysteresis Digital Locked Loop (DLL) Read DQS Skew Read Delay from Rx FIFO DQS Training Control DRAM Bank Interleaving Burst Length (4 beats-8 beats) / 32Byte-64Byte Granularity MTRR Mapping Mode DRAM Voltage VDIMM DRAM VTT Offset DRAM On-Die-Termination CPU VID Control CPU FID Control PCIe clock Bus and Chipset Voltages (RADEON XPRESS Chipsets) Legacy Settings Miscellaneous Comment on This Article
BIOS Settings for the Athlon 64 Platform     including AM2
(MS, June 19, 2006)

The RAS# to CAS# delay is the latency following a bank activate command during which period the data are read out of the memory cells and are latched onto the primary sense amplifiers in the memory cell array. Until this process is completed and the data are stabilized in the sense amplifiers, it is not possible to issue a read command that specifies the retrieval of data at any given column address within the open page.

Functionally, tRCD specifies the waiting period necessary after a bank activate command before a read command can be issued. In low latency memory, tRCD values of 2 is supported but often, a higher latency may be necessary to ensure proper functionality of the memory components. In most systems tRCD has become the most important latency for overall performance of the memory subsystem.

Row Precharge Latency (tRP)

In order to be able to receive a new set of data, the sense amplifiers and the bitlines in a row need to be restored to an empty state, that is, to a state before they are charged with data. Restoring a native, pre-charged state requires disconnecting the wordlines and shorting the complementary bitlines to get rid of any electrical potential between the bitline pairs. If the equalization is not complete, residual charge leftovers from the preceding transaction can falsify the next set of data that are read by the sense amplifiers, thereby causing data corruption and system crashes. Next to tRCD, tRP is the most important latency for system performance.

Unlike the case of CAS# delay, there are no hardware configuration requirements for either tRCD or tRP as long as the minimum time window is satisfied to execute the individual steps involved in each command execution.

Row-to-Row Delay (tRRD)

Modern memory chips have a minimum of four internal banks and each bank is allowed to keep one page open at any given time (unless there is a refresh command underway). Because multiple pages of memory can be kept open, interleaving can be allowed, that is, different rows can be accessed by the memory controller in interleaved fashion. That is, instead of closing one row and opening another row on the same bank, the controller specifies a different row on a different internal bank ahead of time, and then only needs to issue an address to a different internal bank with an open row in order to immediately thereafter issue a read command. There is still a minimum spacing between consecutive bank activate commands. This spacing is called the Row to Row activate Delay or tRRD and is specified in ns values on the memory device level that are translated by the controller into cycles according to the memory bus speed. The lowest tRRD supported in current memory systems is 2.

next page:    => Row Cycle Time (tRC), Row Refresh Cycle Time (tRFC), Read to Write Time (tRWT) and Refresh Rate =>

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