Navigate: Advice Beginners BIOS Guide CPUs Links Mainboards Memory Network Storage Video/Sound Cards Contact Forum SiteMap Sponsors Home PC Hardware from Made-in-China.com Search: Enter your search terms   Web www.lostcircuits.com Submit search form	.
Prices:

LOSTCIRCUITS	SHORTCUTS: LDT & PCI Bus Control / HT Link Control HT Multiplier Configuration HT Width DRAM Configuration Timing Mode (Auto) / SLI-Ready Memory Memclock Index Value (MHz) (200 MHz) Changing the CPU Multiplier Invalidates SLI Memory Performance Options Odd Divisor Correct CAS# latency (tCL) Min RAS# to Active time (tRAS) RAS# to CAS# Delay (tRCD) Row Precharge Latency (tRP) Row-to-Row Delay (tRRP) Row Cycle Time (tRC) Row Refresh Cycle Time (tRFC; tREF) Read to Write Time (tRWT) Refresh Rate Write Recovery Time (tWR) 1T/2T Memory Timing / Command Per Clock (CMD) Read Preamble Value Async. Latency Value)	Async. Latency Value) Dynamic Idle Cycle Counter IdleCycle Limit Read/Write Queue Bypass / Bypass Max Drive Strength Settings DQS Hysteresis Digital Locked Loop (DLL) Read DQS Skew Read Delay from Rx FIFO DQS Training Control DRAM Bank Interleaving Burst Length (4 beats-8 beats) / 32Byte-64Byte Granularity MTRR Mapping Mode DRAM Voltage VDIMM DRAM VTT Offset DRAM On-Die-Termination CPU VID Control CPU FID Control PCIe clock Bus and Chipset Voltages (RADEON XPRESS Chipsets) Legacy Settings Miscellaneous Comment on This Article
BIOS Settings for the Athlon 64 Platform     including AM2
(MS, June 19, 2006)

Historically, the row cycle time has been tRCD + tCL + tRP, meaning a Active to Read latency followed by a Read latency and a Precharge latency. In modern memory components, tRAS is more important than a simple addition of tRCD and tCL. As a result, the minimum tRC value should be no less than tRAS + tRP.

Row Refresh Cycle Time (tRFC; tREF)

Auto Refresh cycle time. DRAM cells lose charge over time and therefore, the contents need to be refreshed by reading them out from the memory cells to the sense amplifiers and then restoring the data in the memory cells of origin. This process requires one entire row cycle time at minimum, however since often more than one row is refreshed by modern controllers, on average, two additional cycles are recommended to complete the refresh in all banks scheduled.

Read to Write Time (tRWT)

Since the memory data bus is bi-directional, reads and writes use the same data lines. This requires that the data are cleared off the data traces before the bus can turn around for example from a read transaction to a write transaction since otherwise data could collide on the bus. Moreover, on each sender and receiver, the input and output buffers need to be turned On and Off, respectively. Since every transaction also needs to prep the bus by sending a preamble or dummy signal across, a turnaround requires a few bus cycles. Lower numbers mean faster turnaround but can also affect the stability.

Refresh Rate

Memory cells are tiny capacitors that are required to hold data for a minimum of 64 msec before they must be refreshed. A refresh involves reading the data out to the sense amplifiers and then writing the data back to the memory cells. In terms of timing, it means that within 64 msec all rows of data have to be refreshed but every row has to be refreshed by itself.

Older memory chips used to have 2048 or 4096 rows per bank, most current chips feature as many as 8192 rows per bank. Therefore, the refresh rate equals 64 ms/8192 or 7.8 µsec (15.6 µsec in a 4096 row design). In other words, every 7.8 µsec, all memory transactions are interrupted in order to refresh one row of memory. Setting the refresh rate to a higher value (for example 15.6 µsec) incurs the risk that the memory cells will have lost their data already and will cause system crashes.

next page:    => Write to Read Delay (tWR), Write Recovery Time (tWR), 1T/2T Memory Timing (1T) / Command Per Clock (CMD) =>

All advice and educational articles on LostCircuits are free, but if you feel you can, please make a small donation to us!
Thank you!

---

General disclaimer: This page only reflects the author's personal opinion and assumes no responsibility whatsoever regarding any of the contents or any damages that may occur explicitly or implicitly from reading the contents of this site. All names and trademarks mentioned in this review are the exclusive property of the respective parent companies.
All contents of this site are protected by international copyright laws. Reproduction of the contents even in parts is not allowed except after written permission by the author and referral to this site.
Copyright 2002 - 2008 LostCircuits