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LOSTCIRCUITS	SHORTCUTS: LDT & PCI Bus Control / HT Link Control HT Multiplier Configuration HT Width DRAM Configuration Timing Mode (Auto) / SLI-Ready Memory Memclock Index Value (MHz) (200 MHz) Changing the CPU Multiplier Invalidates SLI Memory Performance Options Odd Divisor Correct CAS# latency (tCL) Min RAS# to Active time (tRAS) RAS# to CAS# Delay (tRCD) Row Precharge Latency (tRP) Row-to-Row Delay (tRRP) Row Cycle Time (tRC) Row Refresh Cycle Time (tRFC; tREF) Read to Write Time (tRWT) Refresh Rate Write Recovery Time (tWR) 1T/2T Memory Timing / Command Per Clock (CMD) Read Preamble Value Async. Latency Value)	Async. Latency Value) Dynamic Idle Cycle Counter IdleCycle Limit Read/Write Queue Bypass / Bypass Max Drive Strength Settings DQS Hysteresis Digital Locked Loop (DLL) Read DQS Skew Read Delay from Rx FIFO DQS Training Control DRAM Bank Interleaving Burst Length (4 beats-8 beats) / 32Byte-64Byte Granularity MTRR Mapping Mode DRAM Voltage VDIMM DRAM VTT Offset DRAM On-Die-Termination CPU VID Control CPU FID Control PCIe clock Bus and Chipset Voltages (RADEON XPRESS Chipsets) Legacy Settings Miscellaneous Comment on This Article
BIOS Settings for the Athlon 64 Platform     including AM2
(MS, June 19, 2006)

Write Recovery Time (tWR)

In DDR, data are always written to the memory cells with a CAS latency of 1, DDR2 uses Read CAS Latency-1T. However, in order to stabilize the data in the memory cells the equivalent of tRAS (minus tRCD) is necessary, otherwise the data will be lost if a precharge occurs.

1T/2T Memory Timing / Command Per Clock (CMD)

This option sets the Command Rate for the memory controller. At 1T, the controller can issue commands on every clock cycle, if set to 2T, the controller can issue commands only on every other bus cycle. A 2T command rate can be somewhat problematic for a number of reasons. In a first generation DDR architecture, the 2 T command rate can cause bus contention because it can mitigate the advantages of bank interleaving. For example, when using 2:2:2 latency settings, the read command would be issued 2 cycles after a bank activate command. So far so good, according to this there is apparently no need for a 1T CMD rate. However, since bank interleaving allows the opening of several pages in different banks of the same memory device, the second bank activate command that would follow immediately after the first bank activate command cannot be issued because a read command for the first bank is already scheduled. Because of this bus contention, the next possible time slot for the next bank activate command will coincide with the second read command (in case there is a page hit) and so on until there is a no-op (no operation) interval at which the bank activate command can finally be executed. Needless to say that as a result the advantages of bank interleaving are largely negated.

In DDR2 designs, the situation is similar. One of the reasons DDR2 introduced the Posted CAS feature was to eliminate bus contention. That is, instead of waiting for tRCD to be satisfied, the Read command is issued immediately after the Bank Activate command and the necessary latencies are added internally on the DDR2 chip through the "added latency" delay. Needless to say that this feature can only play out its full advantage in a CMD Rate of 1T, especially in a BL=4 burst setting (see below) where the 2 cycle interval between read commands will effectively eliminate any other command because of bus contention.

Read Preamble Value

After any extended idle period, the memory bus has to be cleared of noise signals accumulated from picking up electromagnetic interference. This is done by sending a "dummy signal" called Read Preamble over the bus to flush out the electrical noise. Until the Read Preamble, the DQS receivers on the chipset are turned Off but they will be turned On in anticipation of the assertion of the DQS signal(s) by the memory devices. In other words, it is necessary to make the preamble long enough to allow turning On of the strobe receivers, otherwise, whatever comes down the bus will not be recognized as data.

Async. Latency Value

The asynchronous latency specifies the round trip loop time from the CPU to the farthest DIMM in the memory system and is mostly influenced by the trace length to the memory slots. Other factors that play into the Async. Latency are the memory load and frequency. Recommended values are as follows:

• 9 ns for system configurations of 8 Registered PC 2100 DIMMs,
• 8 ns for Registered PC2700 and PC3200 DIMMs
• 7 ns for unbuffered PC 3200 DIMMs (3 - 4 DIMMs)
• 6 ns for unbuffered PC 3200 DIMMs or faster (1 - 2 DIMMs)

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