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LOSTCIRCUITS	SHORTCUTS: LDT & PCI Bus Control / HT Link Control HT Multiplier Configuration HT Width DRAM Configuration Timing Mode (Auto) / SLI-Ready Memory Memclock Index Value (MHz) (200 MHz) Changing the CPU Multiplier Invalidates SLI Memory Performance Options Odd Divisor Correct CAS# latency (tCL) Min RAS# to Active time (tRAS) RAS# to CAS# Delay (tRCD) Row Precharge Latency (tRP) Row-to-Row Delay (tRRP) Row Cycle Time (tRC) Row Refresh Cycle Time (tRFC; tREF) Read to Write Time (tRWT) Refresh Rate Write Recovery Time (tWR) 1T/2T Memory Timing / Command Per Clock (CMD) Read Preamble Value Async. Latency Value)	Async. Latency Value) Dynamic Idle Cycle Counter IdleCycle Limit Read/Write Queue Bypass / Bypass Max Drive Strength Settings DQS Hysteresis Digital Locked Loop (DLL) Read DQS Skew Read Delay from Rx FIFO DQS Training Control DRAM Bank Interleaving Burst Length (4 beats-8 beats) / 32Byte-64Byte Granularity MTRR Mapping Mode DRAM Voltage VDIMM DRAM VTT Offset DRAM On-Die-Termination CPU VID Control CPU FID Control PCIe clock Bus and Chipset Voltages (RADEON XPRESS Chipsets) Legacy Settings Miscellaneous Comment on This Article
BIOS Settings for the Athlon 64 Platform     including AM2
(MS, June 19, 2006)

Dynamic Idle Cycle Counter

The Idle Cycle Counter keeps track of memory accesses in order to make sure that pages that are being accessed are not closed if activity is interrupted for a few memory bus cycles. This is particularly important when data are loaded into cache and the CPU takes several cycles to process them before requesting the next batch.

IdleCycle Limit

Open memory pages consume substantially more power than closed pages. Moreover, if a memory read request falls onto an address outside of a currently open page, it causes a page miss, which is the worst case scenario for any memory access because the already open page needs to be closed before a new bank activate command can be issued to open the correct page. On the other hand, especially in streaming applications, keeping a page open increases the probability of a recurrent access to the same page, based on the principle of locality of data.

As best compromise between the above mentioned possibilities, the memory controller has to make a decision how long it will keep a given memory page open before it closes it. This decision is based on the probability of another access to the same page (page hit), in which case only the CAS latency would be incurred.

A rule of thumb is that after a certain number of no-operation cycles, no subsequent accesses will occur to the same page, since either, the subsequent data are found in a different location within the memory subsystem, or the data are already in the cache, or else, a refresh cycle is pending. The idle cycle counter specifies the number of no-op cycles that the memory controller will wait until closing the page. Empirically, the best performance is obtained with settings between 16 and 64 cycles.

One thing to keep in mind is that the idle counter values are only relevant if the Idle Counter itself is enabled.

Read/Write Queue Bypass / Bypass Max (4)

AMD's memory controller allows for out of order execution of requests. That is, the execution of older requests can be postponed or queued if they don't fit into the ongoing memory request sequence. For example, writes that would interrupt a read requests can be queued up for execution at a later stage, likewise, if there are accesses to the same page with an intermittent access across the page boundary, the latter can be queued up for execution after all page hits have been serviced.

Because of the time sensitivity of the requests, a limit needs to be imposed of how many times a given request can be bypassed to service higher priority accesses (based for example on locality within the physical memory address space). The recommended maximum for bypassing older requests is 4.

next page:    => Drive Strength Adjustments, DQS Hysteresis, Digital Locked Loop (DLL) =>

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