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LOSTCIRCUITS	SHORTCUTS: LDT & PCI Bus Control / HT Link Control HT Multiplier Configuration HT Width DRAM Configuration Timing Mode (Auto) / SLI-Ready Memory Memclock Index Value (MHz) (200 MHz) Changing the CPU Multiplier Invalidates SLI Memory Performance Options Odd Divisor Correct CAS# latency (tCL) Min RAS# to Active time (tRAS) RAS# to CAS# Delay (tRCD) Row Precharge Latency (tRP) Row-to-Row Delay (tRRP) Row Cycle Time (tRC) Row Refresh Cycle Time (tRFC; tREF) Read to Write Time (tRWT) Refresh Rate Write Recovery Time (tWR) 1T/2T Memory Timing / Command Per Clock (CMD) Read Preamble Value Async. Latency Value)	Async. Latency Value) Dynamic Idle Cycle Counter IdleCycle Limit Read/Write Queue Bypass / Bypass Max Drive Strength Settings DQS Hysteresis Digital Locked Loop (DLL) Read DQS Skew Read Delay from Rx FIFO DQS Training Control DRAM Bank Interleaving Burst Length (4 beats-8 beats) / 32Byte-64Byte Granularity MTRR Mapping Mode DRAM Voltage VDIMM DRAM VTT Offset DRAM On-Die-Termination CPU VID Control CPU FID Control PCIe clock Bus and Chipset Voltages (RADEON XPRESS Chipsets) Legacy Settings Miscellaneous Comment on This Article
BIOS Settings for the Athlon 64 Platform     including AM2
(MS, June 19, 2006)

Memory DQ Drive Strength / DRAM Driver Weak Mode

The I/O buffers of modern memory chips are capable of variable drive strength that can be configured through a mode register set command by setting bit 1 in the extended memory register set (EMRS) register during system initialization. Depending on the memory bus topology, it may be of advantage to adjust the DQ (I/O Buffer) drive strength for best performance. In most cases, the default setting (nominal; not reduced) will be the best option.

DRAM Drive Strength (Normal Drive)

Similar as in the case of the memory I/O buffers, the memory controller can adjust the drive strength according to overall system memory load. That is, with higher system memory density and consequently more memory chips that need to be driven by the controller, higher drive strength is necessary. However, other parameters also play into this setting as, for example, the specific resistor configuration on the memory PCB. For most memory modules, the best value is "normal".

The nVidia nForce5 reference BIOS further subdivides the parameters that can be adjusted according to the different input/output pins on either memory devices or chipset.

• CKE Drive Strength adjusts the memory Clock Enable signal.
• MCLK Drive Strength adjusts the memory clock input strength.
• CS Drive Strength adjusts the chip select signal that is used to turn on the address and command inputs on the selected rank.
• MA Drive Strength adjusts the address and command signal strength, the more physical memory is in the system, the more address and command signal strength is required
• MD Drive Strength adjusts the data output signal strength.
• DQS drive Strength adjusts the data strobe signal strength.

DQS Hysteresis

The DQS hysteresis is essentially a buffer to eliminate fast voltage transients on the data strobe lines (DQS). The DQS is a bi-directional LVDS strobe signal used for clock forwarding. That is, a reference clock signal (strobe) is sent out along with the data by means of the differential strobe pins. The receiver receives the data along with the forwarded clock signal. This clock forwarding scheme mitigates data skew arising from differences in trace length. The clock signal usually carries some fast overshoot transients that can be filtered out by DQS hysteresis. It is not recommended to disable this clock forwarding signal filter since disabling the filter will add substantial noise to the signal.

Digital Locked Loop (DLL)

The digital locked loop controls the relation between the DQS (Strobe) and the DQ (Data). Disabling the DLL can de-synchronize the timing of the strobe and the actual data and should not be done except for debugging purposes.

Read DQS Skew

In a dual channel memory system all data have to arrive at the receiver (memory controller) at the same time. In order to achieve this, it is necessary to adjust the clock skew of the data strobe to take into account the different trace lengths between the memory controller and the corresponding memory slots. Older designs have largely employed snaking of the memory data traces, however, an easier way of getting there is to adjust the data strobes with a differential delay for the two channels. This explains the different timing values for the two memory channels with, for example, the clock skew of channel A being advanced 150 psec further than that of channel B. As explained above, the reason is actually trivial, the physical trace length is different for the two channels and, therefore, the clock skew needs to be adjusted accordingly to compensate.

DQS Training Control

The DDR2 feature set also comprises off-chip driver calibration for the bidirectional differential Data I/O strobe (DQS). This calibration is often referred to as DQS training which happens on system initialization. The nForce5 chipset allows turning on or else skipping of this feature.

Read Delay from Rx FIFO

Once the data strobe receiver gets the DQS Receiver Enable signal, it still needs to get ready to receive the data. A lower latency increases the responsiveness of the system but can result in instability. Vice versa, a longer read delay can increase stability at the expense of responsiveness. On the other hand avoiding error and retry can also substantially speed up the system AND increase stability.

next page:    => DRAM Bank Interleaving, Burst Length (4 beats) / 32/64-Byte Granularity, MTRR Mapping Mode =>

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