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LOSTCIRCUITS	SHORTCUTS: LDT & PCI Bus Control / HT Link Control HT Multiplier Configuration HT Width DRAM Configuration Timing Mode (Auto) / SLI-Ready Memory Memclock Index Value (MHz) (200 MHz) Changing the CPU Multiplier Invalidates SLI Memory Performance Options Odd Divisor Correct CAS# latency (tCL) Min RAS# to Active time (tRAS) RAS# to CAS# Delay (tRCD) Row Precharge Latency (tRP) Row-to-Row Delay (tRRP) Row Cycle Time (tRC) Row Refresh Cycle Time (tRFC; tREF) Read to Write Time (tRWT) Refresh Rate Write Recovery Time (tWR) 1T/2T Memory Timing / Command Per Clock (CMD) Read Preamble Value Async. Latency Value)	Async. Latency Value) Dynamic Idle Cycle Counter IdleCycle Limit Read/Write Queue Bypass / Bypass Max Drive Strength Settings DQS Hysteresis Digital Locked Loop (DLL) Read DQS Skew Read Delay from Rx FIFO DQS Training Control DRAM Bank Interleaving Burst Length (4 beats-8 beats) / 32Byte-64Byte Granularity MTRR Mapping Mode DRAM Voltage VDIMM DRAM VTT Offset DRAM On-Die-Termination CPU VID Control CPU FID Control PCIe clock Bus and Chipset Voltages (RADEON XPRESS Chipsets) Legacy Settings Miscellaneous Comment on This Article
BIOS Settings for the Athlon 64 Platform     including AM2
(MS, June 19, 2006)

Modern DRAMs have at least four internal banks that can be interleaved. Interleaving means that each internal bank can keep one page of memory open to allow subsequent access of data within open pages even if they are in different banks. The advantage is that page boundaries can be effectively masked by moving to a different bank where a Read or Write transaction can be performed while the previous page (in the previous bank) can be precharged in the background and, moreover, a new page can be opened.

Burst Length (4 beats-8 beats) / 32-Byte-64-Byte Granularity

DDR (1) allows in theory burst length of 2, 4 and 8, DDR2 only allows for burst length of 4 or 8. Depending on the burst length specified in the initialization of the DRAM chips, each column address supplied by the memory controller will be received by the column address decoder of the memory chip, which consequently generates 3 or 7 additional column addresses. This cuts down on utilization of the memory command bus but has the drawback of lower granularity. Instead of specifying an 8 beat burst length, the memory controller can utilize back-to-back transactions of a burst length of 4. For the actual data transfer, this is inconsequential, however, the command bus needs to issue twice as many read commands. In most cases, this will not make a difference, however, it is possible that the extra commands needed in a BL=4 scenario will cause bus contention. On the other hand, it is possible that a BL=8 setting will cause unnecessary transactions in order to fulfill the required burst length. The optimal setting will depend on the specific program.

As different way of describing the burst length is the number of bytes transferred with each burst. Since every rank of memory is eight Bytes wide, each transfer equals 8 Bytes as well. Consequently, each BL=4 burst will transfer 32 Bytes, whereas a BL=8 burst will transfer 64 Bytes. Note that this "granularity" definition refers to a single channel, in dual channel mode, the granularity on a system level would be 64/120 Bytes per transfer.

Because of the use of the early read command described earlier in this article, back-to-back bursts of 4 can be performed which look, in terms of data transfer characteristics exactly like a single burst of 8. The difference is that there is one additional read command that needs to be issued in 32-Byte granularity mode, on the other hand, there is less redundancy in case the data requested are less than 128 Bytes (in dual channel mode).

MTRR Mapping Mode

The MTRRs (Memory Type Range Registers) specify memory address ranges with respect to their cacheability or lack thereof. Values are WriteBack, WriteCombining, UnCached, UncachedSpeculative Write Combining. Setting the MTRR values allows the exclusion or inclusion of certain memory address ranges from being cacheable. This prevents cache overflow by data contained for example in the video memory in systems with integrated video controllers. In multiprocessor systems and multi-core processors, each processor has its own MTRRs that can be set as either unified (continuous) or discreet (each CPU has its own memory ranges). For best system performance, continuous MTRR mode should be selected.

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