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Top Page Pitfalls in Parallelism Seven Deadly Limitations (I) Seven Deadly Limitations (II) Tagged Comand Queuing Transitional Solutions SATA Clocking, LVDS and Cabling Staggered Pins For HotSwap Cyclic Redundancy Check Error Detection Seagate Barracuda SATA V Test Setup and HDTach WinBench 98 Business WinBench98 HE Conclusion |
| Seagate Barracuda SATA V Serial ATA and the 7 Deadly Sins Of Parallel ATA | |
| (Review by MS, September 15, 2002) |
Currently, Seral ATA is still in the waste lands, there are still issues between controllers and different drive configurations, some of these issues appear reporting errors of the software used rather than real performance issues but overall, the new technology looks extremely impressive and promising. The results from HDTach are not exactly mind blowing, timing marginalities could play into those numbers as well as some other issues.
One issue that might be relevant for the performance or lack thereof in HDTach measurements of the burst rate is that for the first time, we have a drive and interface that is actually faster than the downstream PCI bus. In other words, a possible scenario is that the drive sends data packets to the controller / PCI bus, fills up the buffers there and sends the next string of data. Everything happens at 150 MB/sec. Potentially, and this is purely speculative, the subsequent burst cannot be handled by the controller because it is still busy trying to funnel the data through the bottleneck of the PCI bus. The consequence would be a retry. By extension, if we spin this a bit further, we would come to expect successful transactions alternating with retries caused by full buffers. This might be a possibility to explain the roughly 50% utilization of the bus only when at the same time, other, nominally slower drives will achieve higher performance. Again, this is pure speculation, without bus analysis tools we cannot answer the question. Another possibility would have been to repeat the HDTach measurement using a 66 MHz PCI card, however, unfortunately, at this time we did not have any external 66 MHz PCI-based SATA controller to test our hypothesis.

Marvel serializer-based SATA interfaces that plug into the HighPoint ATA/RAID controller on the Shuttle AS45GTR
Regardless of whether the hypothesis outlined above is valid or not, the topic opens another issue which concerns the saturation of the PCI bus even with 150 MB/sec transfers. This calls for an independent data bus or else a 66 MHz PCI bus as implemented in the AMD MPX platform. In other words, will SATA 150 or 300 be useless for the average consumer? The answer is: Absolutely Not!
SiliconImage SATA-link on the Iwill P4ES
The reason is buried in the WinBench results. The highest transfer rates that we get are in the order of 57 MB/sec. Of course, those are average numbers and cut off the peak transfer rates but the takehome message is that burst rates are burst rates and even the fastest drives cannot fill up the buffers at the same rate as the buffer can flush the data. Therefore, there will always be enough headroom, at least in the near future.
In the far future, that is sometime next year, we will see SATA controllers with dedicated lines to the NorthBridge like Intel's ICH5 that are running completely uncoupled from the PCI bus. nVidia will have similar technology in their Hammer chipsets as will probably everybody else.
Finally, the last question is whether it is worth migrating to SATA with the new chipsets / boards that are just hitting the shelves and the answer is one unambiguous yes.
Acknowledgements: A number of individuals have been extremely helpful in the making of this article: Marc Noblitt, Seagate; Mark Jackson, Maxtor; Larry Li and Craig Lyons, Promise Technology; Sumit Puri, Fujitsu and most importantly, Joni Clark, Seagate.
Apologies to those whose names have slipped my mind, I know there should be some 20 more acknowledgements and, closing my eyes, I see the faces but cannot remember the names.
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