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For reasons of simplicity and easier calculation of timings, we will be leaving UATA133 out of the picture and concentrate on UATA 100 or ATAPI-6.

Briefly, the ATA standard employs a 16 bit wide bi-directional bus that is capable of transmitting two bytes per transaction. For a 100 MB / sec throughput, this requires a 50 MHz data rate or 50 Mbps (50 Mbit per pin and second). Clock signals are subject to skew and sluggish edges, therefore, from an electrical standpoint, in most cases it is cleaner to use half the frequency with a double data rate protocol that allows transfers not only on the rising but also on the falling edge of the clock. In this particular case, this results in an actual clock frequency of 25 MHz with a cycle time of 40 ns.

Timing diagram for UATA-100, image courtesy of Seagate

Let's stick with the 40 ns bus cycle time for another second. Fourty ns appears long but in reality, the important interval is the time between consecutive clock edges and that translates to ½ of a clock cycle, in this case, 20 ns. These 20 ns need to accommodate setup and hold times as well as the maximum allowable switching times. In other words, every transaction originates at the clock edge and needs to be completed within 20 ns but the data also need to be available for a certain time after the crossover point. This "Hold Time" is specified as 4.8 ns by the ATAPI-6 protocol.

Likewise, there is a time interval before the clock edge during which the data are made ready for transfer, this "Setup Time" is also specified as 4.8 ns. Combined, Setup and Hold times add up to 9.6 ns within an available 20 ns hemicycle, leaving no more than 10.4 ns switching interval. Moreover, the 10.4 ns are applicable only if there is no delay in reaching the Vhigh or Vlow targets, a somewhat unrealistic assumption. In any case, given the fact that setup and hold times remain fairly constant, it is easy to see where the UATA 133 standard with its 15 ns hemi-cycle time (5.4 ns switching time) will be the fastest achievable unless some more fundamental changes are happening.

The counterintuitive aspect of a narrow bus

Moving from a wide bus to a narrow bus is somewhat counterintuitive when it comes to justifying high speed data transfer and overall bandwidth. In other words, if 15 ns hemi-cycle time and 33 MHz clock frequency are already problematic with respect to signal integrity, how can we expect more bandwidth from a narrower bus that would run at multiples of that frequency. In other words, we were just claiming that 15 ns are hard to maintain but now we are postulating that we can make it work at 0.333 ns hemicycle time. Needless to say that Setup and Hold times are shorter but also the maximum available switching time is reduced from 10.4 ns to 0.273 ns. Further, these numbers conform to SATA150 only which is just the beginning. But then, serial designs are shedding the chains of master-slave configurations and even more weight.

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