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There are some fundamental differences between serial and parallel buses, more importantly, there are some critical limiting factors in the design and implementation of any parallel bus.

• 1. Non-Interlocked (source synchronous) clocking
• 2. 3.3 V high-low signaling with 5V legacy tolerance
• 3. Cabling constraints
• 4. Connector legacy
• 5. Termination
• 6. Command queuing
• 7. PCB Design

UltraATA uses a conventional non-interlocked (source-synchronous) clock signaling. This means that an additional clock signal acting as a strobe is sent along with the data. This source synchronous clocking is necessary because of the high propagation delays caused by cable length and trace impedance.

The drawback is still that any differences in electrical properties of the traces can cause a mismatch in timing, i.e., different arrival times for data and strobe signals or even between signals running on separate data lines. This problem is generally referred to as clock skew and directly relates to the signal voltage amplitude.

Fotr those concerned about not having the correct power adapter on their power supply, here is the good news: All SATA drives will ship with power adapters like the one shown here. Picture courtesy of Seagate

2. 3.3 V High-Low Signaling

The issues with 5V used up to the UDMA 33 standards regarding clock skew caused the industry to change the standard to 3.3 V signaling. The main advantage is a more symmetrical distribution of the high-low voltages around the 1.5V trip point. Keep in mind, though, that 3.3V still means massive charges traveling down the ribbon cables

3. Cable Design Issues: Cross-Talk and Ground Bouncing vs.Ringing

Each signal propagating through a data line makes the data line act like the inductor of a transformer. That is, each voltage swing generates a dynamic electromagnetic field, that, depending on cable length and proximity will induce another signal in adjacent data lines. This cross-talk adds noise to data lines and can produce errors by generating false positives or negatives simply by induction of voltage swings in data lines.

Another problem with parallel pathways is the phenomenon of simultaneously switching outputs (SSO) noise. As we explained in detail in our reviews of the i845 and the SIS645 chipsets, SSO noise becomes really problematic if the majority of signals switch from high to low since this can induce ground bouncing. On the chipset level, workaround in form of dynamic bus inversion (DBI) is feasible, that is, instead of switching all bits, only the reference bit is switched simultaneously at the sender and receiver end which has the same net effect, namely, that the system does not see the reference switch but thinks that all other lines have switched. DBI, however requires an additional latency cycle and this is where the 40 ns clock cycle time starts to look really ugly.

Workaround

In the past, the easiest way to remedy cross-talk has been to minimize cable length. However, in most cases, this solution is simply impractical. With older UDMA cables it was still possible to custom cut the cables and add a custom connector. Our own experience with those cables (some 4 inches) has been that they greatly increase overclocking tolerance, performance and reliability of any drive.

From a commercial standpoint, a more feasible solution turned out to be the addition of interlaced ground wires to add shielding between data lines. The standard ribbon cable, therefore, uses an additional 40 wires that connect through the existing seven ground wires within the 40-pin connector. This interlacing of signal, power and control lines (throttle, SMART etc. since the real control signals are, as mentioned above time-muxed over the data lines) with ground wires effectively eliminates electrical cross-talk.

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