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Termination of 4 signal lines used in SATA is a no-brainer compared to termination of the 32 signal lines in parallel Ultra ATA. SATA also supports so-called active impedance matching circuits that can match almost any cable to any device and, thus, allow greater flexibility in cable design and length.

6. Tagged Command Queuing

True SATA devices will incorporate TCQ even though it will become mandatory only with SATA II

7. PCB Trace Routing Issues

The constraints and requirements are the same as in parallel ATA, however, only four traces have to be implemented on the mainboard instead of 32 traces in the case of parallel ATA. This equation is not quite correct since in parallel (Ultra) ATA, each channel supports 2 drives whereas serial ATA is limited to one drive per connector / channel. Still, support for four drives will require a total of 16 traces as opposed to 64 traces in the current parallel format.

The PCB trace routing issues go, however, far beyond the point of making the PCB designer's life easier. The real issue here is that with four traces per connector, it is possible to add a practically unlimited number of connectors to the layout where unlimited means the number of ports supported by the I/O controller. Current controllers support 2 or 8 ports, upcoming solutions will feature four ports (Promise, Intel). Additional connectors can be added by using PCI-extension cards.

8. Cyclic Redundancy Checking (CRC) Error Detection

Cyclic Redundancy Checking (CRC) was introduced originally with SCSI Ultra160 technology to improve data integrity. CRC is probably the most significant benefit of SATA.

CRC allows error detection on both the protocol and the interconnect layer. To make a long story short, error detection is handled at the PHY (signal and 10-bit stream problems, no device and PHY internal errors), the link layer (10-bit stream, data integrity or invalid state errors) and the transport and software layers. Errors in each layer are visible to each other layer. Statistically, the efficacy of CRC error detection is such that at a constant 100 MB/sec a triple error would slip through the detection scheme every 4.7 * 10^18 years, about 1 million times the existence of our solar system from origin to black hole.

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