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LOSTCIRCUITS
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| Intel Pentium4 3.46 Extreme Edition / 925XE chipset | |
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(Review by MS November 16) |
| Intel P4 560+ At: |
Memory Performance
ARGUABLY, WE were running a bit out of spec here since we set in both DDR2 platforms the latencies to 3:3:3:8 (CL:tRCD:tRP and tRAS) at 533 MHz data rate whereas most specs call for either 4:4:4:12 or even 5:4:4:13 latency settings. To make a long story short, relaxing the timings to 4:4:4:12 gave us on average an approximately 4-5% performance hit and there is really no point in going there anyway since there are enough memory modules out there capable of sustaining the lower latencies. On the other hand, using higher latency modules made things downright ugly performance wise.
Cachemem 2.65
Memory access latencies for the 925XE at 1066 MHz host bus frequency (solid bars) compared to the 925X running at 800 MHz (transparent bars). in both cases, the memory frequency was 533 MHz data rate at 3:3:3:8 [t] latencies. At higher stride length and consequently an increased number of page misses we see a gain of almost 10% in data access for the new 925XE chipset running in pseudo-synchronous mode as opposed to the original 925X version that needed to translate the data from a double width 533 MHz memory bus (effective 1066 MHz) to an 800 MHz interface. Keep in mind that the CPUs used here are both ExtremeEditions with a low latency pipeline.
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Intel P4 Northwood 2.4 (hard to find) |
Memory Bandwidth
As long as we were running SiSoft Sandra, the system behaved as expected ... sort of, at least.
Sandra 2004 SP2
There is clearly an improvement of the 925XE chipset over the older 925X chipset. However, as we alluded to earlier, there are also differences between the different CPUs, i.e. Northwood / Gallatin vs. Prescott. Not only that, but there is also a difference between the 560 and the 550 processor.
Basically the same picture as above and we might have missed something, had we left it at that.
next page: => Memory Performance Part II =>
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