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LOSTCIRCUITS	SHORTCUTS: A Process Shift Brisbane by Numbers Test Configurations Memory Subsystem Power Consumption 3D Rendering and Power per Renderpass POV-Ray- Cinebench AV-Encoding 3Dmark'06 F.E.A.R. DOOM3 FarCry L2 Cache Latencies The Plot Thickens Final Thoughts Give Us Some Feedback on this Review
AMD's Brisbane Core - the Transition to 65 nm And the cache latency
(Author: MS, January 5, 2007)

Cache Issues - Or Not?

Shortly after the initial reports on the 65nm processors, we saw two reports on TechReport and AnandTech, showing a disproportional increase in the Level2 cache access latency from approximately 12 cycles to 20 cycles - a whopping 67 % increase in access latency! Shortly thereafter TechReport offered an explanation based on some reply from AMD regarding this issue. Bottomline here was that the increased cache latency was supposed to be a measure to accomodate future increases in cache size.

Tom Ting Wen Wong

... was the name the Chinese couple gave their black baby. We have the same feeling about the reported 67% increase in cache latency since there is no logical explanation why any extension of the SRAM address space should go over board with latencies as shown in the graphs. Moreover, as shown in the earlier part of this article, there is no system performance equivalent of the increased cache latency. Even a walk through the cache as done in e.g. TechReport's Linpack analysis shows less than 10% decrease of the cache bandwidth, which, under the circumstances should translate into roughly a 10% increase in access latency.

We compared the posted data to our own data obtained with Cachemem 2.65 and, interestingly enough, we did not see the humongous increase in cache latency.

Cachemem, in this case showing the X2 5000+ (90 nm) (solid) and the X2 4800+ (65 nm) (transparent) shows the main memory being slower due to the lower frequency and also shows a small increase in L2 latency - in the order of approximately 10%. Latencies are given in [ns], lower is better!

To get to the bottom of this, we re-ran Cachemem with a number of different speed grades of both cores and instead of plotting the entire memory system, we are concentrating on the cache portion only

According to Cachemem, there is on average a 2 clock cycles delta in access time between the 90 nm (solid) and the 65 nm (transparent) cache

As mentioned on the first page of this article, different benchmarks will give different results, depending on how well the cache controller understands the workload. On the other hand, there may also be a different kind of explanation

next page: => The Plot Thickens =>