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Above, we have talked about registers but what are registers anyway? In general, registers are dedicated, very small, amounts of ultrafast memory that are used to hold data temporarily and forward them on the next clock edge with a single clock cycle delay. This ultra-low latency makes the registers the fastest part of any data holding, memory or storage subsystem, faster than the L1 or the L2 cache with their 3 cycle latencies and, therefore, they are an integral part of the performance food chain. Without the registers, there would be a lot of READs or WRITEs (LOADs and STOREs) to the cache. Wider registers, that is, in this case, the 64 bit GPRs provide a greater dynamic range, that is, the data range is, at least theoretically increased by a factor of 2^32 or 4.3 billion over the 32-bit registers.

In practice, this widening of the data path will only result in somewhat limited benefits for performance, even the increase of the addressable memory beyond the 4 GB boundary is only "interesting" unless some other synergistic measures are taken as well. The 32-bit ISA is confined to eight 32-bit GPRs, that is, eight 32-bit integer data can be held for immediate processing. AMD's x86-64 ISA quadruples this "register space" by increasing the width from 32 bits to 64 bits and, simultaneously, doubling the number of GPRs from 8 to 16. At the same time, the number of 128-bit vector registers for SSE, SSE2 and similar extensions has also been doubled from 8 to 16. It is of purely academic value but taken together, the total register size within the x86 architecture is 1280 bits and this number almost triples to 3072 in the x86-64 ISA. And again, nobody would care if it weren't for the fact that more data can be delivered faster and in a more efficient manner to the processing units, which, in turn, results in better performance, everything else being equal.

Doubled has also the instruction pointer (IP), commonly referred to as program counter (PC) from 32-bit (EIP) to a 64-bit program counter. Addressing can be done in RIP-relative mode, that is by adding a 32-bit signed integer to the 64bit RIP of the next instruction.

Everything else being equal also includes the operating system, that is, running a 64-bit processor on a 32bit operating system which will be, at the current state of things, the main focus of the benchmark section in the second part of the review.

To summarize, the major improvements over the legacy x86 ISA include:

• Sixteen 64-bit general-purpose integer registers to quadruple the GPR space compared to the eight 32-bit registers in the x86 ISA.
• Sixteen as opposed to eight 128-bit XMM registers for enhanced multimedia performance to double the register space of any current SSE/SSE2 implementation.
• 64-bit virtual address space with 52 bits of physical memory addressing that can support systems with up to 4 petabytes of physical memory - more than one million times the amount of memory supported by 32-bit x86 systems. In the first iterations, the Athlon 64 and Opteron will support only 48 bit virtual memory and 40 bit memory addesses, though, meaning that the amount of supported physical memory increases by 256x from 4 GB to 1024 GB (1 Terabyte). This, by far surpasses the 64 GB physical memory space enabled by Physical Addressing Extensions (PAE) enabled by some server class 32-bit x86 processors.

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