|
Advice Beginners BIOS Guide CPUs Links Mainboards Memory Network Storage Video/Sound Cards Contact Forum SiteMap Sponsors WebNews Home |
. | . |
Prices: Mainboards ABIT ASUS Chaintech Shuttle Soyo Tyan CPU Intel P4 2.4C-800 P4 2.6C-800 P4 2.8C-800 P4 3.0-800 P4 3.2-800 AMD AthlonXP XP 1700+ XP 2000+ XP 2400+ XP 2500+ XP 2700+ XP 3000+ XP 3200+ Athlon64 Athlon64 3200+ Athlon64 FX-51 Opteron Opteron 240 Opteron 242 Opteron 244 Opteron 246 Memory Corsair Crucial Kingston Mushkin OCZ |
The Memory Controller
The Athlon64 as opposed to the Opteron was originally planned as just an Athlon64, that is, the 64 bit core, a single HyperTransport interface and, more importantly, a single 64bit memory interface. In the final instance, today, we are looking at the Athlon64 FX-51, which is essentially an Opteron 1xx, that is, an Opteron with support only for a single processor platform, however, sporting dual channel memory controllers. Dual channel configuration of the memory controller, in turn, requires use of Registered DIMMs that add certain latencies. Additional limitations are trade-offs between system memory density and frequency.
All current chip formats used for system memory are supported, that is 4, 8 and 16 bit chip width, the main reason for the support of the x4 format being that it allows the use of stacking technology to achieve module densities of up to 4 Gbytes. Within a single module, bank interleaving is supported and the burst length can be set to either 32 bytes (BL=4; Single Channel Controller only) or 64 bytes. What is interesting is that despite the fact that up to 16 physical banks are supported (with 4 internal banks each), the number of open pages across the entire array can only be 16 at the time while the entire array can contain up to 64 pages.
In order to maximize the efficiency of the open pages, the precharge (page policy) control can be set to dynamic mode to make intelligent "on-the-fly" choices regarding the page policy based on the page-hit/miss history. In thus far, the 16 open pages appear more than sufficient.
Registered, Unbuffered, ECC and Scrubbing
The Opteron as well as the Athlon 64 FX-51 require Registered DIMMs and are capable of performing ECC. Keep in mind that Registered and ECC are features that are completely independent from each other.
A Registered ECC DDR module using TBGA packaging, conforming to the latest JEDEC standards. The module features two TI registers (one on each side) and its own ICS clock generator (one per module)
A register is, as briefly touched upon above, an intermediate holding station for data in whatever form. In the case of Registered DIMMs, the register is an extra chip that receives address and command data from the memory controller and then redistributes those data on the next rising clock edge to the individual chips on the module. The advantage is that the memory controller is completely agnostic of now many chips are on the module, all it sees is a single register per Rank. This way, the capacitative load on the controller is very low because all the work is done by the register. The drawback in this case is that there is an additional wait state that will increase the initial access time (tRAC).
The difference between a register and a buffer is that a buffer can propagate the signal within the same clock cycle, however, this will cause some sluggishness of the signals, the best known examples for this type of buffer were the address translator chips used on some ABIT and SuperMicro boards in order to expand the number of supported DIMM slots.
The name unbuffered is, therefore, technically correct since unbuffered DIMMs do not have a buffer but in reality, it misses the point since the relevant term would be un-registered.
ECC or Error Checking and Correction is a method to find and correct errors based on Euclidian findings recently rediscovered as "Berlekamp-Massey" algorithm. Suffice it to say that ECC needs additional bits, which is the reason for the total bus width increase to 72 bits. Amongst the features supported under the general umbrella of ECC is also what is known as scrubbing. Scrubbing means that the entire array of memory is continuously checked for soft errors and that ECC algorithms are used in order to correct those errors as soon as they occur, for example as a consequence of cosmic rays.
For a normal household or workstation, "ECC scrubbing" is completely superfluous. Soft errors caused by cosmic rays occur approximately 1 / 3 months and 1GB of memory and any shut down of the machine will deplete the volatile system memory of its data anyway, including errors. In so far, there is absolutely no reason to use scrubbing at all. Scrubbing, in combination with chip-kill has, however, significant value in machines that are running 24-7 over several months / years since in this case, especially with large amounts of memory, an accumulation of soft errors could occur that could either cause programs to crash or else cause data corruption. The capability of the Athlon 64 FX to perform scrubbing, therefore, needs to be viewed as legacy from its workstation and server ancestors.
next page: => Latencies =>
