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Bye, Front Side Bus
Most of us who have been around long enough have come to adapt the term front side bus or FSB as something that characterizes the interface of the CPU with the memory controller. Without being picky, the term FSB has been applicable only to Slot1 and SlotA processors that actually featured a Back-Side Bus to the on-board L2 cache, hence the distinction of a front-side vs, a back-side bus. Ever since the return of the socketed format, the term FSB has been obsolete or rather a misnomer but like most historical heritage, it has been hard to kill and even those who never witnessed a true FSB use the term to describe the processor to system bus interface as well as the external CPU clock.
In the case of the Athlon 64 / Opteron, the wildest definitions have been spotted floating around, particularly when it comes to overclocking. In reality, the clocking scheme is rather simple, there is a reference clock derived off a quartz that drives the CPU, while other signals are branching off to drive the PCI and HyperTransport as well as the AGP bus. Keep in mind here that changing the external CPU reference frequency will not have any impact on the HyperTransport, which, in most cases, will be frequency-locked. Neither will the AGP or PCI frequency and either of their derivatives be changed. What is changed solely is the external CPU clock, which, naturally, also changes the memory controller operating frequency (since the memory controller is an integral part of the CPU) and the memory bus interface frequency.
Clock logic diagram including the "stop" for unused devices and the Spread Spectrum Modulation in order to reduce EMI detection. Each subsystem of the clock tree can be modulated independent of the other branches, meaning that e.g. the HyperTransport will not be altered if the CPU is overclocked, just as one example.
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