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| AMD's AM2 Platform DDR2 ... Moving On | |
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(Review by MS May 23, 2006) |
Summary
The industry is not always governed by the rule that the best technology may prevail, rather it is the least expensive solution that often wins the market, regardless of performance. Along these lines, DDR2 has evolved to a more cost-effective memory architecture than the original DDR with the additional forward-looking advantages of possible higher densities without the need of going to registered address and command interfacing. Combined with signalling frequencies in excess of 2 x of the original specifications, DDR2 has finally come to maturity and - in view of the mentioned frequency bumps, it can even compete on the turf of latency with the fastest DDR designs.
Some 4 years after the initial announcements, it therefore appears as if DDR2 is finally going mainstream and just as Dell finally accepted AMD, AMD finally accepts DDR2. Coincidence? Or a way for Dell to get rid of their DDR2 inventory? And whatever happened to performance?
The Delay
When we posted – about 3 ½ years ago - the first comprehensive preview of an emerging memory technology called DDR2, we were somewhat skeptic about its general acceptance, and that, regardless of the fact that, at that time, DDR2 was designated to be the one-size-fits-all solution to memory and bandwidth problems. Despite all pushes from Intel and the different memory vendors, it took multiple generations and speed grades for DDR2 to reach price and performance parity with the older, first generation DDR design. In the end, it was no less than 42 months later until DDR2 was accepted to the point where both Intel and AMD supported it on their platforms.
DDR2: A Match for NetBurst
In retrospect it is easy to see where the NetBurst architecture pushed by Intel along the evolutionary path of Pentium4 processors had nothing to lose by migrating to the less expensive DDR2 design with the additional benefit of higher bandwidth - yet at the expense of latencies. With its own rather massive latencies, the Intel bus interface negates any latency improvements on the memory level anyway. On the other hand, SSE, SSE2 and SSE3 instruction sets with their inherent simplifications of instructions and optimization of streaming data applications were largely designed to effectively work around those latencies and utilize bandwidth as much as possible.
AMD: The Low Latency Strategy
Whereas Intel – carrying over a little legacy from Rambus – was pushing bandwidth over latency, AMD's Athlon64 family went off into a completely different direction. The integration of the memory controller into the actual CPU die resolved a number of different issues, amongst others the problem of latency caused by a memory controller running at bus speed only, the AGTL bus latencies and, maybe more importantly, the issue of cache snooping necessary for any bus master in order to verify the validity of data requested from main memory. Since the memory controller is on-die, any address placed on the bus can snoop the cache and with essentially no turnaround time, can be propagated to the memory array in case the data are not in the cache and have not been modified. At the same time, the memory interface as integral part of the CPU also allows, at least in theory, that a request is directly served by the cache. The latter also finally provided a justification for the modification of the MESI protocol to a MOESI variant with the "O" - as in owned - specifying exactly that type of operation.
It is inherent though that low latency controllers will be hurt by high latency memory devices, since the latter will mitigate the performance gains of the faster controller.
The AM2 socket uses 940 pins. Left: FX-62; right X2-5000. All current dual core models are based on the "Windsor" core with either full or half L2 cache, the single core versions are based on the "Orleans" core and comprise both Athlon64 and Sempron versions
The Surgery
Another issue has been plagued the acceptance of DDR2 by AMD. As put rather fittingly by Joe Macri (ATI) - who coincidentally (co)invented DDR2 and DDR3 - a memory controller integrated on the CPU level could easily turn into a suicide feature since any change in memory architecture and protocol necessitates a substantial redesign of the CPU and, at the minimum, a new set of wafer masks. However, in their infinite wisdom, the fathers of the current AMD processor family placed the memory controller onto the die in such way that it could easily be removed and replaced by a more recent version. Along these notes, it is worth pointing out that the same controller should be able to handle DDR2 AND DDR3, meaning that the next change in memory architecture may only require the blowing of some fuses.
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