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| AMD's AM2 Platform DDR2 ... Moving On | |
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(Review by MS May 23, 2006) |
Commodity Pricing and DDR2 Market Acceptance
Nothing influences the market as cost as, for example, the Intel/Rambus combo had to experience in a rather painful manner. Cost, in the situation at hand, though, is the biggest asset of DDR2 compared to DDR. A core running at only ½ speed of the I/O is cheap to manufacture; if price parity is applied, the interface frequency (I/O frequency) can almost be doubled and the granularity of bursts will at that point become a largely negligible issue. From the viewpoint of DRAM manufacturers used to literally wrapping $-bills around every single IC sold for almost half a decade, a low cost solution like DDR2 in combination with the novelty factor and associated mark-up, therefore, appeared to be the ticket to ride into found-again profitability.
Needless to say that in the big Samsung/Infineon/Micron et al. picture, the issue about AMD being at a disadvantage with DDR2 only caused a marginal ripple. Given the other problems - including Rambus and hefty fines for price fixing - the lack of altruism and sympathy for AMD is not particularly surprising.
Loads and Densities
To be true, there are other factors playing into the big push for DDR2. One of the most critical factors causing DDR performance limitations is the issue of load on the address and command bus. On a system level, DDR2 is at a clear advantage here because of the added feature set of off-chip driver calibration that eliminates the guesswork associated with adjustments of drive strength. Similarly, the skew between different ICs on the same module and between different modules is taken care of by means of the bidirectional differential strobe that warrants extreme precision in signal timing both upstream and downstream.
Microsoft and Memory Requirements
The above mentioned idiosyncrasies of DDR2 weigh in even heavier in a forward-looking situation. Microsoft Vista with its extreme demand on physical memory space almost forces the migration to either registered modules or else to a DDR2 design. Everything else being equal, the latencies will become comparable but DDR2 will still incur the advantage of higher bandwidth. With increasing operating frequencies, also the latency problem becomes less and less of an issue. Arguably, latencies of four cycles always look ugly, on the other hand, in raw nanoseconds, a 4:4:4 IC running at 800 MHz will have the exact same latencies as a 2:2:2 IC running at 400 MHz. Likewise, at 800 MHz, a command rate of 2T will be almost the same as a 1T CMD rate at 400 MHz. Not quite though, since one of the novel features of DDR2 is the "Posted CAS" and "Added Latency" strategy which builds on sending a read command on the next clock cycle after the bank activate command. If the command rate can only use every other cycle, the result is a CAS latency that is pushed out one cycle further than specified, in other words, a CAS-4 part will actually incur 5 latency cycles. Likewise, bank interleaving that effectively uses the gaps within a given command sequence is going to take a minor hit in streaming applications.
2 x 1 GB will be the minimum requirement for running Microsoft Vista - at least if minimum performance expectations are to be met
In a nutshell, for all reasons mentioned, in the long run, the migration to DDR2 was inevitable but inevitability does not alleviate the burden on AMD of how to cope with the situation at hand. Naturally, admitting the weakness, would have been a bad PR move, the final acceptance of DDR2 had to come at least at performance parity. In all fairness, straight from the Texan horse’s mouth we never heard anything going beyond that. On the other hand, rumors regarding miraculous performance advancements surfaced like fungus after a rainy day, only to be dispelled by preliminary beta results and their lesser qualified propagules. In the end, rumors and nebulous information took a bit of wind out of the pre-release expectations but there are still enough facts that are worth writing about.
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