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| AMD's AM2 Platform DDR2 ... Moving On | |
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(Review by MS May 23, 2006) |
Memory Subsystem
With a new memory architecture, the obvious questions are naturally about the theoretical performance and then the extrapolation of the results into real world applications. As generally accepted, even theoretical memory performance is based on two separate components, that is, raw bandwidty and latency. The first can be calculated rather easily from the bus width and frequency, in a dual channel DDR2 800 configuration, the theoretical peak bandwidth equals 128bit x 800 MHz or 12.8 GB/sec. In the latest iterations of the older DDR architecture, the peak bandwidth at 400 MHz was 6.4 GB and a good system could always reach real values in the order of 6 GB/sec - equivalent to roughly 90-95% bus utiliazation.
In the case of the new AM2 architecture, DDR2 results in a slight increase in streaming memory bandwidth, however, compared to the theoretical maximum of 12.8 GB/s, the real world performance of ~7.1 GB/sec only amounts to some 56 % bus utilization. Still, the overall memory bandwidth is higher than even the theoretical maximum of the DR400 standard in the first generation DDR architecture.
Latency
In the introduction, we mentioned that, because of the higher frequency and lower clock cycle time, the actual latencies of a DDR2-800 system should be close to that of a DDR-400 system. On the other hand, at DDR2-800 we did not succeed to maintain a CMD rate of 1T, which adds latency particularly in a page miss situation where another open row can be accessed through bank interleaving. This scenario is likely to happen in predictable page boundary crossing as it would happen in large block transfers at a predefined long stride.
Since we had two Windsor cores with both full and half caches, we compared them to the Toledo and the Manchester core, respectively. For simplicity reason, we only show the data at DDR2-800 vs. DDR400
FX60 vs. FX62 (both 2.8GHz)
FX-60 (solid) vs. FX-62 (transparent): lower is better
X2-3800+ vs X2-5000+
X2-3800+ (solid) vs. X2-5000+ (transparent): lower is better
As long as the stride length is kept below the page size (4KB), the DDR2 platform holds up admirably well with only a 10% increase in access latency of the main memory compared to the DDR400 configuration. However, whenever each access is a page miss, the latency increase of the DDR2 platform reach 25% (FX series) and 30% (X2 series). Whether this is a realistic scenario for real world performance is a question, though.
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Athlon64 X2-3800+ (dual core) |
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