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| AMD Athlon64-FX60 At the Turning Point | |
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(Review by MS January 10, 2006) |
| AMD Athlon64 X2-3800+ (Manchester) |
HyperThreading to MultiCores
To spin this a bit further, the situation does not lack a certain amount of irony since the very optimizations that enabled HyperThreading are now what makes AMD's line of dual core processor so successful. At least compared to Intel's current lineup that still relies on the 8086-derived host bus to interface with the core system logic and specifically with the memory controller. Not only is this host bus bi-directional, meaning it can only read OR write at any given point, but also, it is shared between all logical processors. Given the fact that also every single busmaster First Party DMA access needs to utilize the very same bus for ensuring that the data in the main memory space are valid and not resident and modified in the cache (by virtue of a process called snooping), it is almost inconceivable how the architecture with its inherent latencies can even support the current processing power of high-end CPUs. The actual pipeline length of the Prescott / Cedar Mill becomes almost secondary in view of the just mentioned system interface limitations.
This is where AMD's full duplex HyperTransport or LightningDataTransport makes a difference not only for the current generation of CPU but also for future revisions that will push the sheer insatiable hunger for data another notch up. Reads can be executed in parallel with writes, a simple FP-DMA request will be snooped at CPU speed instead of chipset clock rate and even the arbitration of data is executed in the system request interface at CPU speed.
Fast execution on the front end requires, however, a fast backend, and this is where the battle in memory land will become quite interesting. Before long, we will see the transition of AMD, too, towards the DDR2 architecture, driven primarily by cost considerations since DDR and DDR2 pricing has reached parity and, in the near future, will see DDR2 undercut the first generation DDR pricing. Arguably, DDR2 is slower on the level of latencies, on the other hand, the higher densities of memory discreets allow for higher system memory configurations. Another side effect of the higher discreet density embarks on the fact that 1Gbit and higher memory chips use eight internal banks as opposed to the four banks used on DDR and lower density DDR2 chips.
The importance of the increased number of internal banks is the concurrent increase in open pages that can be maintained, meaning that starting with the M2 interface, we will see a doubling of supported open pages per memory slot from currently 8 (dual rank modules) to 16 (if supported by the memory components). Whether this will really make a performance difference remains to be seen, predictably, however, it will have quite an impact on memory power consumption, especially in interleaved accesses.
There is no action without reaction, though, and exactly the just mentioned increase in power consumption has been the reason for the introduction of yet another memory latency dubbed tFAW (four way access window) that will disallow back to back transactions for the simple reason of preventing thermal runaway within the memory chips.
At this point, all we can say is that another turning point is coming up with new technologies and new rules for new possible configurations. With all due respect for academic considerations of the performance swings in the one or the other direction, there is currently no telling how it will all pan out in the end - not even for us here.
Things to come are interesting enough to get carried away with speculations, right now, however, we are still stuck with legacy hardware, meaning DDR1 for the dual core Athlon64 in its latest revision, introducing the FX moniker to the dual core series.
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Athlon64 X2-4200+ (dual core) |
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