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AMD's Phenom Processor - Beyond Erratum 298
(Author: Michael Schuette, January 1, 2008)

AMD Phenom Tech Specs

Per aspera at astra

ACP, AMD's New Metric for Power Consumption

ACP is AMD's newest addition to the ever growing family of acronyms, designating the term Average CPU Power as a new measure for power consumption that shall replace the Thermal Design Power. The rationale behind the new ACP metric is that customers and engineers do not need to abide by the same power specifications, as long as the engineers use TDP for the design of the platforms, customers can get a more educated idea about the power requirements by using the ACP metric. In a way, this makes sense, as long as the ACP does not exceed the values that we are measuring under load. Based on our measurements, this could turn into a very close call as we will show later in this article.

Phenom's Memory Controller

The memory controller of the Athlon 64 family has had its pros and cons. Running on the CPU at core speed, the actual memory frequencies were derived from a divider of the core frequency. Because of the limited number of integers between 5 and 10, the actual memory frequency was in most cases lower than what was specified in the BIOS or by the memory SPD. Needless to say that there were scenarios where this led to wasted performance. Also, despite the fact that the two channels could act semi independent from each other, a Read was always a Read and a Write always a Write.

Concurrent Reads and Writes in Dual Independent 64-bit Channel Mode

Whereas the Athlon 64 "dual channel" allowed for combination of two 64-bit wide memory channels to a 128-bit wide "superchannel", using linear 64+64 alignment or else byte-level interleaving (IIRC), the Phenom memory controller is far more sophisticated with respect to the protocols supported. Aside from the standard 2 x 64=128 bit scheme it is possible to "ungang" the two memory controllers to independently access individual sets of data. In unganged mode, each controller can serve one or several CPU cores to load data, more importantly, the controllers can be programmed to execute reads on one channel while performing writes on the second channel.

As mentioned, in the Athlon 64 generation, the memory controller always ran at clock speed and the memory clock was derived by means of a divisor. The memory controller in Phenom has its own power/voltage control and its own clock (independent of the CPU frequency). This has three significant implications:

• 1) The memory controller maximum frequency specification is a constant and separate specification apart from the CPU max specification and model specific
• 2) All Phenom processors, regardless of the CPU frequency, run DDR2 memory at the proper specified frequency.
• 3) A significant portion of the CPU's power consumption will be attributable to the memory controller in a frequency-dependent manner.

Memory Support

The documentation on this subject is rather nebulous but supposedly, current Phenom processors will be capable of supporting DDR3 based on the platform infrastructure and recognition of the proper bit in the memory SPD. The official version by AMD is that DDR3 will be supported starting with the release of the 45nm process stepping of the Phenom family.

Backwards Compatibility

Phenom processors have the same pin-out configuration as the AM2 version of the Athlon 64. Athlon 64 "AM2" processors will run on Spider platform boards, courtesy of the dual-mode voltage regulator module.

(AMD Phenom 9600 2.3GHz (HD9600WCGDBO))

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