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LOSTCIRCUITS
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| AMD's Phenom X4 9850 - Silicon Revision B3 | |
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(Author: Michael Schuette, April 6, 2008) |
B3 Silicon, the -50 Series
The latest silicon spin, dubbed B3 is the core of the -50 series of processor in which the problem with the TLB bug has been eliminated. Currently, no information has pulclicly been disclosed, how the issue was addressed, that is whether the existing silicon was tweaked to allow for stable operation above the previous threshold frequency or whether there were more fundamental changes put in place, most likely the latter happened. Whatever was done, though, appears to have worked, at least there is no more requirement to run on a crippled platform. So far so good, particularly in the desktop space this may be more than adequate and the -50 series will phase out the original Phenom as soon as inventory is turned over. Otherwise, nothing really has changed, thermal and power numbers are still the same and the official release of a 2.6 GHz version as in the promised Phenom 9900 or a potential 9950 based on silicon revision B3 is still outstanding.
What remains is what has been announced awhile ago, namely the fact that AMD is following in ATI's footsteps by releasing a "Pro", er, X3 series of CPU, in which only three cores are functional. Interestingly even with three cores only running, there is, at least officially, no reduction in the Max TDP. But then again, specs are specs and reality sometimes teaches otherwise. Interestingly, all currently listed X3 SKUs are based on the B2 silicon revision and, therefore, lack the -50 moniker. The only surviving X4 model number based on B2 is a new "low power" equivalent to the Athlon64 BE series, dubbed in this case 9100e and running at a tame 1.8GHz core speed with the NorthBridge at a further reduced 1.6GHz. Since the TLB-bug is at least to a certain degree frequency-dependent, a low-power, low frequency offering has to be a perfect solution for the B2 Silicon inventory without summoning the wrath of Austin's legal eagles.
This should wrap up the background of the mass release of the world's first native quad and triple core CPUs, we have specific details on the individual models in the following comparison tables.
AMD Phenom X4 9850 processor TECH SPECS:
| Processor Frequency: | 2.5GHz | L1 Cache Sizes: | 64K of L1 instruction and 64K of L1 data cache per core (512KB total L1 per processor) | L2 Cache Sizes: | 512KB of L2 data cache per core (2MB total L2 per processor) | L3 Cache Size: | 2MB | Memory Controller Type: | Integrated 128-bit wide memory controller * | Memory Controller Speed: | Up to 2.0GHz with Dual Dynamic Power Management | Types of Memory Supported: | Support for unregistered DIMMs up to PC2 8500 (DDR2-1066MHz) | HyperTransport 3.0: | One 16-bit/16-bit link @ up to 4.0GHz full duplex (2.0GHz x2) | Total Processor Bandwidth: | Up to 33.1 GB/s bandwidth | Packaging: | Socket AM2+ 940-pin organic micro pin grid array (micro-PGA) | Fab location: | AMD's Fab 36 wafer fabrication facilities in Dresden, Germany | Process Technology: | 65-nanometer DSL SOI (silicon-on-insulator) technology | Approximate Transistor count: | ~ 450 million (65nm) | Approximate Die Size: | 285 mm2 (65nm) | Max Ambient Case Temp: | 61o Celsius | Nominal Voltage: | 1.2-1.3 Volts | Max TDP: | 125 Watts |
AMD Phenom X4 9750 processor TECH SPECS:
| Processor Frequency: | 2.4GHz | L1 Cache Sizes: | 64K of L1 instruction and 64K of L1 data cache per core (512KB total L1 per processor) | L2 Cache Sizes: | 512KB of L2 data cache per core (2MB total L2 per processor) | L3 Cache Size: | 2MB | Memory Controller Type: | Integrated 128-bit wide memory controller * | Memory Controller Frequency: | Up to 1.8GHz with Dual Dynamic Power Management | Types of Memory Supported: | Support for unregistered DIMMs up to PC2 8500 (DDR2-1066MHz) | HyperTransport 3.0: | One 16-bit/16-bit link @ up to 3.6GHz full duplex (1.8GHz x2) | Total Processor Bandwidth: | Up to 31.5 GB/s bandwidth | Packaging: | Socket AM2+ 940-pin organic micro pin grid array (micro-PGA) | Fab location: | AMD's Fab 36 wafer fabrication facilities in Dresden, Germany | Process Technology: | 65-nanometer DSL SOI (silicon-on-insulator) technology | Approximate Transistor count: | ~ 450 million (65nm) | Approximate Die Size: | 285 mm2 (65nm) | Max Ambient Case Temp: | 61o Celsius | Nominal Voltage: | 1.2-1.3 Volts | Max TDP: | 125 Watts |
| Phenom Model No: | CPU Freq. | MC & HT(x2) Freq. | Max TDP | Availability on 3/27/2008 | Price | Core Count | Silicon Revision | Unlocked Multiplier "Black Edition" | ||
| OEMs Only | Channel Only | Channel + OEM | ||||||||
| X4 9850 | 2.5GHz | 2.0GHz | 125W | Yes | $235 1KU | 4 | B3 | Yes | ||
| X4 9750 | 2.4GHz | 1.8GHz | 125W | Yes | $215 1KU | 4 | B3 | |||
| X4 9750 | 2.4GHz | 1.8GHz | 95W | Yes | OEM Price | 4 | B3 | |||
| X4 9650 | 2.3GHz | 1.8GHz | 95W | Yes | OEM Price | 4 | B3 | |||
| X4 9550 | 2.2GHz | 1.8GHz | 95W | yes | $195 1KU | 4 | B3 | |||
| X4 9100e | 1.8GHz | 1.6GHz | 65W | Yes | OEM Price | 4 | B2 | |||
| X3 8600 | 2.3GHz | 1.8GHz | 95W | Yes | OEM Price | 3 | B2 | |||
| X3 8400 | 2.1GHz | 1.8GHz | 95W | Yes | OEM Price | 3 | B2 | |||
All Phenom cores feature 64kB L1 and 512kB of L2 cache, the 1MB L2 version is not available in the multicore version. However, we have noted a few times that there is very little performance increase to be had by going from the half cache to the full cache design in the case of AMD's architecture, whereas the die size penalty is quite substantial. More importantly, since the individual cores cannot talk to each other's L2 cache, a larger L2 would cause more contention because of the higher amount of duplicate / dirty entries. In so far, we don't miss the full cache at all especially since the shared 2 MB L3 cache makes up for the difference anyway.
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