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LOSTCIRCUITS
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| AMD's Phenom X4 9850 - Silicon Revision B3 | |
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(Author: Michael Schuette, April 6, 2008) |
B3 Silicon Memory Subsystem
In the beginning of this article we hypothesized about the effect of a hierarchy of patches and work-arounds and mentioned our suspicion that enacting an increased workload on the BIOS level and then negating it on the level of the OS cannot be the same as just having a pure, unadulterated performance configuration.
Since we have to accept at face value that there weren't really any other changes in the B3 silicon revision, we assume that the differences between a Phenom X4 9850 and a Phenom 9900 in memory performance can solely be attributed to the patch (or lack thereof). For starters, we look at the latest version of Sisoft Sandra to see what happens to the memory bandwidth.
SiSoft Sandra Memory Bandwidth Benchmark
It is pretty obvious that there is a significant performance increase of the 9850 compared to the 9900 or the 9600. The numbers we see in the case of the 9850 are further roughly equivalent to those we got with a pre-patch BIOS on the ASUS M3A32 MVP-Deluxe.
Cachemem Memory Latency
Bandwidth is one thing, latencies are another important performance measure of the memory subsystem. In order to make sure that we are not comparing apples and oranges, we ran cachemem with the 9850 overclocked to a 13x multiplier, that is 2.6 GHz to have identical runtime conditions for both 9900 and 9850.
Memory subsystem access latenciesw, lower is better. The 9850 (solid blocks) shaves off about 5-10% of memory access latencies compared to the 9900 (transparent blocks) in "red" overdrive mode.
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