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LOSTCIRCUITS	SHORTCUTS: How many Hoover Dams? Isolating Power Dual Stress Liner Venice Improvements Test Conditions Power/Temperature Coefficient Idle vs. Burn-In 3D Rendering 3DMarks DOOM3 and Prime95 Overclocking & Conclusions Give Us Some Feedback on this Review
AMD Athlon64 "Venice" May Low Power be with you!
(Review by MS May 2, 2005)

Frequency Caps and Manufacturing Process

The first 3800+ processors based on the NewCastle core were usually clocking up to 2600 MHz but that was where it quickly ended. The 4000+ / ClawHammer cores did a bit better on average, pushing 2.8GHz in most cases with standard air cooling. Then came the die shrink to 90 nm interconnect with a core voltage lowered to 1.4V. as we have seen quite a few times in the past, the first IC revisions after any die shrink are often somewhat slow compared to their predecessors. The original Thoroughbred cores fit right into that scenario. The second Thoroughbred core with an added metal layer and additional decoupling capacitors for noise suppression resolved the issues and turned out to be speed demons that often enough reached clock speed in excess of 3GHz.

With the Winchester core, history appeared to repeat itself. Blessed with relatively little headroom, the highest officially released Wincester core speedgrade was the 3500+ running at 2.2 GHz. The original Winchester cores were manufactured using the 90 nm copper interconnect process on the relatively simple Silicon Germanium epitaxy process for straining silicon but still using SOI technology (see below).

We have covered the theory behind strained silicon at length over a year ago here. Briefly, the original IBM approach featured a relatively simple gradient-based SiGe epitaxy, meaning that the growth of the silicon crystallines on the germanium gradient tries to mimic the structure of the substrate. Because of the different lattice size, the silicon would get stretched – with the side effect of increasing conductance.

         

Si-Ge Epitaxy, uniaxial techniques for straining silicon, compressed strained pMOS process flow (Pictures 2 & 3 Courtesy of Intel Corp.)

The original approach has two shortcomings, first, the stretching of the silicon lattice is bi-axial with the result that current is propagated across the gate as well as orthogonal to it without directional preference. Usually this is not really a problem since the thickness of a die is negligible to begin with. On the other hand, being able to define a preferred transmission direction is certainly a plus and exactly that can be achieved by uniaxial strain. One other anomaly of silicon relates to the fact that n-channels are abiding by different rules than p-channel transistors. In general, n-channels are smaller, cheaper and faster than p-channels and transfer twice the power under equal circumstances. In order to maintain a somewhat balanced power picture, it is mandatory to keep a balance between pMOS and nMOS, likewise, inverters require the presence of nMOS AND pMOS devices. P-channels, on the other hand, are not gaining much from tensile strain as it is realized by the Si-Ge epitaxy. On the contrary, p-channels are speeding up with compressive strain. To give credit where credit is due, Intel has pioneered the differential strained silicon technology with compressive strain on the pMOS and tensile strain on the nMOS transistors.

All of this is fine and dandy in theory, in practice, however, the problem is often enough how to implement the theoretical knowledge reliably into a manufacturing process and this is where the AMD-IBM joint venture bears friut. In short, it is a two step process that can be applied either way by depositing first a tensile Si3N4 liner and etching the PMOS areas to apply a compressive Si3N4 liner or vice versa. The entire process is comparable to painting a checkerboard, whether you start with a white area and then apply the dark squares or you do it the other way round hardly matters. What matters is the result that is fit to be carried over to the next 65 nm process that will probably go into production sometime in 2006 using the same dual stress liners on Silicon-On-Insulator technology as the CPUs manufactured today.

Overall, the IEDM (International Electronics Device Meeting) white paper claims a 24% increase of speed at the same power consumption, we have some reservations about the specific numbers but to give the benefit of the doubt, there are differences between theory and pratice.

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