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AMD today released the "Barton" core-based Athlon XP3000+, featuring a 512 KByte L2 cache and, thus, increasing the overall cache size by a whopping 70% to a total of 640 KBytes. Concomittant with the increase in cache size came a reduction in clock speed but does it really matter? Moreover, what are the applications that will benefit from the larger cache? And finally, will the larger cache hurt the overclocking potential? We think not... We only had 1 1/2 days to play with the processor and write the review but it sure is impressive, the CPU, that is ...

Several months ago we mused about the legacy of the Socket A and the 32 bit processors for AMD, and how the ongoing commitment to the existing platforms were the most logical ways for AMD to not only open up new market segments but also to reassure the existing clientele that they are not just ex and hop as soon as a more lucrative business opportunity comes up. In other words, if customers loyalty is worth anything to AMD, then it should be reciprocated by ongoing and continuing support from the manufacturer towards the existing customer base.

Palomino XP2100+, Thoroughbred XP2200+ and Barton XP3000+
Note the elongated core of the Barton where the additional 256KB Level2 cache have been added.

The concept is nothing new, processor upgrades are amongst the easiest modifications of any system with virtually no hassle compared to any other upgrade except for memory. Since there are no additional drivers to be installed and no registry hacks necessary, and, moreover, there is no question of whether there will be compatibility problems with existing hardware, it is as easy as removing the heat sink, pulling up the locking mechanism and replacing the older processor with the latest model after which the entire procedure will have to be repeated in reversed order.

The result is going to be a doubling of performance, maybe not that dramatic but after a year or so on the same CPU, it could actually happen, at least in applications where the CPU is the bottleneck. This is particularly true if there are some fundamental revisions to the processor that go beyond just a die shrink. The last time we were looking at such radical improvements was during the transition from the Thunderbird to the Palomino core that, as we showed, yielded up to 90% performance increase over the earlier version, courtesy of the implementation of SSE instructions.

The current jargon even within the circles of the less inaugurated regarding processor technology has evolved to adapt a substantial number of buzz words over the past year or so. IPCs and QuantiSpeed along with HT and Screaming Syndee II are being thrown around in almost any discussion revolving around performance. The presence of a multi-tiered cache is usually acknowledged but it is its mere existence rather than the actual cache size that garners attention. Any argument to the contrary is usually being dismissed with the referral to the internal CPU pipelines and / or the fact that the K6-3 L2 cache only thrived on the size of the on-board L3 cache, haven't we heard this over and again in the past months?

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