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Why are we going into this at all? Barton is a revised version of the Throroughbred core with twice the size of the L2 cache. Instead of 256 KB L2 cache, Barton brings 512 KB to the table to increase the total cache size from 384 KB to 640 KB. Keep in mind that these are KiloBytes and not MegaBytes, so why even bother. The answer is very simple. A cache is a dedicated high-speed memory that is running at multiples of the operating frequency of the main or system memory frequency and usually uses a non-multiplexed SRAM interface with minimal access latencies. Any increase in size will increase the probability that data that are needed will be contained within the cache and won't have to be retrieved from the system memory.

Combine the larger cache size with any branch prediction or effective prefetch algorithms either on the level of the chipset or the processor through a dynamic adaptive speculative preprocessor (DASP) like found on the nForce2 and chances are that there will be some major benefit. The operational principles are actually rather simplistic. DASP analyzes incoming data streams for common patterns and cross-references them against the workload. Recurrent patterns are flagged before being returned to main memory. If similar workloads come up during the same session, the flagged data can be speculatively retrieved and stored either in dedicated buffers on the chipset or else they can be preloaded into the processor's cache. It should be obvious that in such a case, even a modest increase in the CPU cache size may yield a disproportionate performance increase, depending on what fraction of essential data for one application can be stored in the additional cache space.

Fact vs. Fiction
On the left is the Thoroughbred core, the yellowish die in the center is the Photoshop art we posted some 8 months ago as what we thought the Barton core would look like, the ochre die on the right is the real thing.

Keep in mind that since usually several applications and services are running in the background, there is an offset involved here. A simple example would be a 256 KB L2 cache where 128 KB are occupied by essential processes or the operating system, leaving another 128 KB for the application at hand. Exceeding the cache space will cause the need for invalidation or eviction of the cache in order to store the new data. Doubling the L2 cache will, in this case triple the amount of high-speed memory available for the particular application running. Keep in mind also that this is only an abstract example, there are other factors like set-associativity that play into cache miss or hit probabilities but as always, theory is theory and practice is practice.

Shortly after the introduction of the Thoroughbred core, rumors about the cache organization were surfacing showing floor plans of the new revised die. We had our own speculations and posted a hypothetical montage based on the Thoroughbred core, which we deemed the only cost economic solution for the Barton core. This was eight months ago.

Lately, I have been asked over and again why I thought that the Barton was going to be a key element in AMD's strategic business and technology plan. The answer is very simple, amongst all improvements that can be done to the current generation of processor, the cache is the most significant factor. Performance hinges on the availability of data and, regardless of the DRAM speed, main memory is falling behind every time the CPU multiplier is increased. Cache speed is independent of the CPU multiplier since it runs at processor clock speed. Granted that there are certain limitations as well in form of the SRAM core speed and the associated latencies, the cache is still the very fastest data and instruction source for the processor execution units. And size matters.

Since we had only about 48 hours to come up with this review, without further ado, let's dig right in.

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