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The new revision of the nForce2 based on the C1 revision silicon of the SPP guarantees functionality at or above 200 MHz , where earlier boards were struggling at 200 MHz and clocking tales were spun around the capacitor and power FET brands, the C1 revision is pretty much fool proof. There is a catch to that situation, that is, enhanced clocking capabilities are bought with some performance hits since some of the chipset latencies needed to set to more relaxed settings, regardless of refined silicon or not. It is important to keep this in mind when comparing overclocked older nForce2 scores with native C1-based builds.

Benchmarking Issues

A number of other issues are important to keep in mind when comparing benchmark scores. For once, WindowsXP supports the advanced programmable interrupt controller (APIC) using MPS version 1.4 (as opposed to version 1.1 used by NT3.51 and below). Briefly, APIC is a distributed set of devices that form an interrupt controller by connecting to a local APIC bus. APIC systems can expand to several hundreds interrupts and, thus, completely avoid sharing of IRQs. A case in point is Windows 2000 / XP that, with APIC enabled, will show 24 IRQs instead of the classic 15 or less interrupt lines.

On the nForce2 chipset, it appears as if enabling APIC per se leads to some performance hit in I/O intensive applications since the system apparently prefers to run the old-fashioned 8259 PIC. The drawback is a less flexible assignments for interrupt requests. Most likely, higher access latencies for the individual devices in APIC mode compared to the more rigid IRQ assignment without APIC are responsible for the difference.

APIC ENABLED: There are 24 different IRQs possible (0-23) and there should be no sharing. However, at least if System Information reports correctly, some of the lower IRQs are not used at all (odd numbers) whereas there is still heavy sharing between e.g. the IDE controller, the USB and the 3Com Ethernet controller.

APIC DISABLED: Only 14 IRQs are available and those are shared between devices. Note that the assignment of IRQs is very different from the above, especially interesting is the fact that the IDE controller is using IRQ #5 instead of the classical #14 / #15 for the primary and secondary IDE channels

Feature sets vary from chipset to chipset and from platform to platform. Bottom line is that with APIC enabled, more devices are supported without IRQ sharing, without APIC, more sharing is involved but devices that have been assigned their own exclusive IRQs or else employ intelligent resource sharing may work faster. In the case of the nForce2 chipset and nVidia SW -IDE drivers, the earlier chipset versions would not even support APIC if the drivers were loaded, causing a complete crash of the system unless the drivers were completely uninstalled. Bottom line is that the system will run certain applications faster without APIC. Keep in mind that switching from APIC enabled to disabled mode does require a complete reinstallation of the operating system.

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