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At this point, there are not enough data on the IBM Power4 available to get into a more detailed comparison, instead, we have a short description of the HP PA-8800. Instead of trying to redesign everything from scratch, HP has taken two existing PA-8700 cores and combined them to the new PA-8800 (internal code name Mako).

The internal core architecture is not completely out of the ordinary, core features are the dual integer ALUs, Shift/Merg units dual FP Units for floating point multiplication and accumulation as well as separate dual FP Units for the divisions / square roots.

Functional diagram of the individual PA-8700 RISC cores with their instruction fetch, sort/scheduling and execution units..

The Floorplan

Three hundred million transistors take up quite a bit of real estate. Considering that each bit of conventional SRAM uses 6 transistors, 3 MB of on-chip alone require 150 million transistors which make any current Intel or AMD processor look pale in comparison. In addition to the four blocks of instruction and data cache, there are 25 million transistors for the core and the rest is easily allocated in the form of tagRAM for both L1 and L2 cache (1 MB for L2 tagRAM alone) plus a minor portion going into L2 and bus control.

Over 1/2 of the entire real esate of the PA-8800 is occupied by the L1 cache blocks alone. Another large chunk goes to the tagRAM keeping track of the addresses of data and instructions in the L1 and L2 caches. The individual cores "only" contain some 25, million transistors, roughly equivalent to most current high-end desktop processors..

Functional Considerations of a 2-in-1 Design

Having two separate cores on the same die enables 2 x multiprocessing by a single CPU. For desktop applications this is rather irrelevant, however, in a server and / or workstation environment, MP capabilities are almost a must. Sharing the L2 cache already eliminates the issue of L2 coherency and only requires direct arbitration of the L2 access between the cores. There is still, however, the problem with the L1 cache which requires simultaneous coherency lookups between the two L1 data caches and the L2 cache. For the record, there is no direct data passing between the two L1 data caches.

Functional diagram of the "SMP" core of the PA-8800 RISC processor..

Servers operate in an environment dictated by mostly random memory accesses which is one of the reasons why e.g. Rambus technology would have a hard time to perform in a server. In the kind of server that the HP PA-8800 is designed for, even access of a low latency memory for every single access is not fast enough which is the reason why the processor relies on a 32 MB L2 cache with ECC checking. At the current state of technology, it is impossible to incorporate such an amount of cache into the CPU die. Therefore, the L2 has been moved off-chip but remains on the same card, similar as what was done with the original PentiumII / Athlon Classic. The remote location notwithstanding, a 32 MB pure SRAM would mean a huge die of over 1.8 billion transistors total with a projected cost of some US$ 2,000 at best. This price tag alone could potentially kill the entire project right there. A possible workaround is the so-called 1-Transistor SRAM.

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