Navigate: Advice Beginners BIOS Guide CPUs Links Mainboards Memory Network Storage Video/Sound Cards Contact Forum SiteMap Sponsors WebNews Home	.	.
Prices: Mainboards ABIT ASUS Chaintech Shuttle Soyo Tyan CPU Intel P4 2.4C-800 P4 2.6C-800 P4 2.8C-800 P4 3.0-800 P4 3.2-800 AMD AthlonXP XP 1700+ XP 2000+ XP 2400+ XP 2500+ XP 2700+ XP 3000+ XP 3200+ Athlon64 Athlon64 3200+ Athlon64 FX-51 Opteron Opteron 240 Opteron 242 Opteron 244 Opteron 246 Memory Corsair Crucial Kingston Mushkin OCZ Search Prices:

1-Transistor-SRAM

In the true sense of the word, SRAM means Static RAM (Random Access Memory) meaning that the data are stored in the form of logical transistor states. This is in contrast to DRAM using capacitors that lose charge over time and need to be refreshed by a combined read-write in order not to lose data. In addition, the operation of a DRAM can best be described as a Destructive Read because any read occurs in the form of a capacitor discharge that depletes the cell of its information. Thus, the data are destroyed and need to be written back to the memory cell before the bank is closed in order to restore the original data content. There are some other distinctions to the classical definition of SRAM as well, though. DRAM or dynamic RAM uses a multiplexed address bus. What that means is that row and column addresses are passed through the same address pins in a time multiplexed manner, in other words, the row addresses come first, then the same address pins are re-used to generate the column addresses. An SRAM interface works differently in that the row and column addresses are specified simultaneously, which dramatically shortens access latencies, albeit at the cost of doubling the address pins (separate pins for row and column addresses). The non-multiplexed addressing and the speed of SRAM complement each other since the logical state of a transistor can be read instantaneously, while the same addressing scheme in a standard DRAM part would not result in increased performance since the physical process of sensing the voltage differential is too slow. Therefore, address multiplexing actually matches the speed of DRAM and does usually not cause any performance hit but saves address pins.

SRAM is composed of either four or six 6 transistors per bit. DRAM, on the contrary only needs one single capacitor per bit with one gating transistor. On the other hand, DRAM technology has come a long way, meaning that hybrid technologies have been created using the higher pin-count SRAM interface to implement SRAM architecture using and ultrafast DRAM core with its lower component count, footprint and last not least price tag. The result is the so-called "1 Transistor SRAM".

1 Transistor SRAM (A Retro Term)

A "1 Transistor SRAM" is basically a paradox and describes a technology that originated in the 1980s as Pseudo Static RAM. One Transistor SRAM indicates SRAM pinout, functionality and timing while the cells use DRAM technology. For the record, "1 Transistor SRAM" and "Pseudo Static RAM" are synonymous even though the industry has begun adopting the term 1 Transistor or 1 T SRAM over the Pseudo Static RAM name. It still does not preclude 1T SRAM from having to restore the data after a read and needing the periodical refresh in order to retain data.

On the other hand, the system sees the memory equivalent to an SRAM, that is, row and column addresses are given in a non-multiplexed manner via separate address pins. The advantage is an initial access time getting close to an SRAM with the footprint and, more importantly, cost factor of a DRAM. The disadvantages are that DRAMs are still marginally slower than SRAM and further need to be refreshed once in awhile. On the other hand, refresh penalties are in the order of less than 1% and, therefore, are negligible.

600 MHz data rate low latency 72Mb DDR ESRAM as L2 - Building Block

A case in point is the Enhanced Memory Systems 72 Mb ESRAM used as the L2 cache for the HP PA-8800 processor. Four of these chips are placed on the same PCB as processor core for 32 MB total L2 cache size. The discrepancy between 4 x 72 Mbit and 32 MB cache size originates in the additional check bits required for ECC.

3D illustration of the 72 Mbit ESRAM chips. Using an ultrafast DRAM core combined with an SRAM interface for "broadside" (non-multiplexed) addressing, the chips are packaged in BGA packaging using a 209 pin layout.

Each chip is organized into several blocks for dispersion of power and heat. Every read command fires up 4 blocks simultaneously using block-interleaving and each block reads out 2 x 18 bits that are pipelined using 4:1 time multiplexing into 9 I/O buffers. While the data are output, a prefetch running in the background captures the next set of data that are pushed into the I/O buffers to provide seamless transition to the next databurst of 4 words (each word = 4 bytes or 32 bit + ECC). At 600 MHz data rate, this translates into 36 bit every 1.66ns per chip. Since the L2 cache consists of 4 chips that are accessed simultaneously, the total burst rate is 128 bits / 1.66 ns or 9.6 GB/sec bandwidth plus the required ECC checkbits.

next page:    => Clamshell Explained =>