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Four Chips to Fill the Bus

The L2 interface of the HP 8800 RISC CPU is using a 128 bit + ECC wide bus and needs 4 chips of 36 bit I/O interface each. Conventional solutions have often placed cache chips side by side as shown below. This arrangement is the probably easiest solution for QFP packaging where the connects are limited to the periphery of the chips.

Conventional layout of a 4 chip "off-die" L2 cache as it was used on some mainboards in the past using Quad Flat Pack. One example of a QFP packaging with the lead-out at all four edges of the chip is shown on the right

Mostly for reason of controlled impedance, high speed memory chip packaging is moving away from QFP packaging to a BGA format. Contacts are no longer at the periphery of the chips but underneath which has the advantage of having a ground plane nearby to eliminate inductive crosstalk. The BGA packaging has some additional advantages.

Face-To-Face in a Clam-Shell

Clam-Shell mounting describes putting two chips face-to-face on opposite sides of a PCB using through-hole connections as illustrated in the cartoon below.

ATwo chips are facing each other on opposite sides of the PCB using the same throughole connectors. Therefore, pins facing each other are electrically connected to allow sharing of power and ground as well as addresses. To separate data from one chip and the other, no-connects are interspersed with data pins as shown in the next figure.

An Almost Real-Life Example

On the left is the simplified pinout of the 72 Mb ESRAM chip with the data I/O pins in yellow, address pins in blue, core voltage in red and I/O voltage in green. Black pins are no-connects. The trick is to build a symmetric backbone of shared voltage and address pins in the center of the array so that (in this case, the red, green and blue) pins come to lie on each other even if the chip is flipped horizontally. The yellow data pins, however, alternate with the black no-connect pins. The detailed pinout can be found here .

On the right, the resulting pin-overlap is shown. Data I/O Pins are connected to no-connects on the other chip since the contacts pass through the entire width of the PCB. Core, I/O voltages, ground and addresses are shared between both chips. This is about as simple and cost effective as one can possibly design a multi-chip array using low impedance traces.

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