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Adding the Cache to the Processor

One picture tells more than a thousand words: cross section through the back-end of the PCB with two ESRAM chips mounted in clamshell configuration.

Cross section of the real thing: The two chips are on both sides of the PCB and are interconnected by vias or through-holes.

As shown above, always two ESRAM memory chips are mounted face-to-face on the 9.6 GB/sec L2 cache interface of the HP PA-8800 processor. With four ESRAM chips, the result looks as follows:

Approximation of what the final HP PA-8800 RISC processor will look like.

System Interconnect and Performance Expectations

The fastest processor is useless without an adequate system bus. The HP PA-8800 uses a 200 MHz double-pumped (400 MHz data rate) 128 bit data bus interface with source synchronous clocking and a total bandwidth of 6.4 GB/sec. The data bus is using ECC while the address bus uses parity protection. According to the current industry standards, the bus supports pipelined transactions and out of order completion. The interface is 100 % compatible with the Intel Itanium processor family (IPF) bus. This by itself allows interchangeability with Intel's next generation CPUs to upgrade to higher performance and single chip SMP if necessary. Speaking of performance, each PA-8700 RISC core delivers a SPEC performance of around 550 (for both Int and FP) at 750 MHz and the dual core PA-8800 running at 1 GHz will start out at a minimum of 900 / 1000 SPEC2000 int/fp scores, according to very conservative estimates. In terms of server performance, this translates into an estimated minimum of 800,000 tpm (transactions per minute) and puts the PA-8800 RISC processor at the top of its class.

Special Thanks to David J. C. Johnson for some of the material used in this article.

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