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LOSTCIRCUITS	SHORTCUTS: PR-elude to the afternoon of a processor Mommy! Look, No Pins DDR2 Briefs Power Plays Sandra vs. Aida Cachemem 2.65 A Neat Analyser Intermission... Give Us Some Feedback to Help Us Improve our Reviews
Intel LGA775 SocketT New and (Un) improved?
(Review by MS, July 28, 2004)

DDR2, Bandwidth over Latency

We have covered DDR2 in more detail almost 2 years ago in this article that goes into the technical details as well as making some performance predictions. Since we don't expect everybody to dig through eight pages of high-tech stuff, here is a short recapitulation of the basic features of DR2.

Slow Core, Double-Speed I/O, 4 x Data Rate

The essence of DDR2 is the fact that a slow core can be used that, on every clock after a read command is issued, prefetches four bits (per I/O pin) from the memory array according to the addresses generated internally on the DDR2 die's logic part. Those bits are then stored in I/O buffers and released in either "interleaved" or else "sequential" mode which specifies the internal sequence (and has nothing to do with either page or bank interleaving as known from BIOS settings).

The result is that the I/O part of the memory device can run at double the speed of the core, which makes it much easier to crank up the speed and, in addition, by using a DDR I/O protocol, the device can actually output (or receive) four transactions per core clock cycle as illustrated in the diagram below.

Single Data SDRAM, DDR (1) and DDR2 side by side to illustrate the relation between core frequency and data rate.

This is really pretty much all what DDR2 is about. The rest is basically enabling the new technology, features like posted CAS and On-Die-Termination ODT) as well as Off-Chip Driver calibration (OCD) are window dressing to keep the journalists and end-users in awe. The main advantage of DDR2 over the first generation DDR is the higher bandwidth which, albeit, is bought at the expense of increased latencies. The second aspect of DDR2 is the higher passive current leakage, caused by the "Center-Tap" termination scheme used in DDR2, but all of this is negated by the lower production costs for DDR2. The latter aspect is offset by the higher profit margins of the DRAM manufacturers, at least for the time being.

             

DDR2 DIMMs are very similar in appearance to the original DDR modules, however, the key is off, making it impossible to insert DDR modules into DDR2 slots and vice versa. It takes a bit more familiarity to spot the finer pitch resulting in 240 pins as opposed to 184 pins in DDR2 and DDR, respectively. The modules provided used special Micron discreets to meet Intel's stringent performance criteria for the platform launch. Two DDR2 modules "in action", that is, in dual-channel configuration.

One peculiarity of DDR2 is that the new chips are manufactured only in BGA format, and no longer internally feature a "lead frame" but rather use wirebonding to a laminate substrate. From a functional perspective, the new packaging technology does not offer any real advantage, in the best case, roughly 200 pico seconds can be shaved off but since DDR2 uses a clock forwarding scheme, actual delays are not as critical as the chip internal skew of the individual I/Os. The latter can be matched independent of the packaging format. Potentially, a real breakthrough could be achieved with the move to a flip-chip interconnect but such technology is not specified for DDR2 and may come with DDR3 in the future.

ICH6

The second new aspect of the Intel 9xx platform is the second generation Serial ATA enabled for native command queuing (NCQ).. Keep in mind that NCQ does not work with bridge drives but requires native SATA drives such as the latest generation of Maxtor Maxline III or the Seagate Barracuda 7200.7 or, the Fujitsu BH series. Unfortunately, in the current form, the ICH6 only supports NCQ in RAID formations but not on single drives.

The latest and greatest in Intels series of I/O controller hubs is the ICH6-R as featured on the reference boards

On the other hand, the Intel Matrix Storage Technology is extermely impressive in that it allows flexible configuration of RAID arrays in ways that were unthinkable before. Specifically, Matrix Storage Technology allows to partition two drives with two partitions each and then run two partitions in a RAID Level0 (striping) configuration and the second pair of partitions in Level1 (mirroring).

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