Navigate: Advice Beginners BIOS Guide CPUs Links Mainboards Memory Network Storage Video/Sound Cards Contact Forum SiteMap Sponsors WebNews Home	.	.
Prices: Mainboards ABIT ASUS Chaintech Shuttle Soyo Tyan CPU Intel P4 2.4C-800 P4 2.6C-800 P4 2.8C-800 P4 3.0-800 P4 3.2-800 AMD AthlonXP XP 1700+ XP 2000+ XP 2400+ XP 2500+ XP 2700+ XP 3000+ XP 3200+ Athlon64 Athlon64 3200+ Athlon64 FX-51 Opteron Opteron 240 Opteron 242 Opteron 244 Opteron 246 Memory Corsair Crucial Kingston Mushkin OCZ Search Prices:

LOSTCIRCUITS	SHORTCUTS: PR-elude to the afternoon of a processor Mommy! Look, No Pins DDR2 Briefs Power Plays Sandra vs. Aida Cachemem 2.65 A Neat Analyser Intermission... Give Us Some Feedback to Help Us Improve our Reviews
Intel LGA775 SocketT New and (Un) improved?
(Review by MS, July 28, 2004)

Summary

The long-awaited Intel 925 / 915 platform has finally hit the channels and it brings more innovation to the table than any other platform in the last decade. PCI Express formerly known as 3GIO, fully functional SATA, a new memory platform and all of that paired with a new speed stepping of the Pentium4 -- with a complete facelift and a a new socket. "Look Mommy, no Pins" is the latest advertising slogan, er, we made that one up...

From a design standpoint, there are distinct advantages and disadvantages to the new components and interfaces, vaguely comparable to curing the bubonic plague with a broadsword. In other words, there are many shifts in paradigms and much novelty but are changes really all for the better or will they only move some critical issues away from the spotlight into the chiaroscuro of marketing glitter?

We spent some time with the new platform, then came new drivers and we spent some more time with the new platform and before there are more new drivers, we thought we finally put together a series of articles dealing with the different aspects of the Intel 9xx platform, including the $64,000 question "How does it perform". We'll go through it step by step, though.

A New Platform

Hardly any architectural change in the last decade has been as radical as the makeover wrought upon us by Intel a few weeks ago. AGP no longer suffices to feed the bandwidth-hungry graphics adapter, rather, we need PCI Express formerly known as 3GIO or 3rd generation I/O standard, DDR is too bandwidth-limited to keep up with the processor and had to be replaced with DDR2, processor pins are all of a sudden obsolete. In the middle of all these radicalisms are some more evolutionary changes like the final enabling of native command queuing for Serial ATA devices. Most of the architectural changes mentioned do not encompass any backward compatibility at all but do require a completely new set of peripherals.

             

Intel's new chipsets and reference boards: Left to right: D925XCV --- PCI-E slots Close-Up: the graphics card interface uses PCIe 16x whereas the two small PCIe slots are 1x only. For backwards compatibility, Intel stuck four standard "legacy" PCI slots onto their D925XCV board --- D915GUX.

The two cases in point are the new DDR2 memory and PCI Express as the new graphics interface. With respect to the latter, PCI Express increases the available bandwidth from the AGP 8X interface running at 2 GB /sec to a whopping 4 GB/sec, equivalent to a hypothetical AGP 16x interface. On the basis of the memory access path, this requires a bus width translation from a 128 bit memory interface to a 16 lane bi-directional PCI Express bus and back with the necessary schedulers and combiners in place.

What is PCI Express Anyway?

PCI Express is only a new name for what was originally known as third generation I/O interconnect. Briefly, instead of a parallel interface with separate command and address buses in addition to the actual data bus and a shared bus topology, 3GIO proposed a high-speed, low pin count serial interface that routes CAD (Command, Address and Data) packets similar to the transfer scheme used in networking environments using a point to point connection. The main difference is that there is no longer a shared bus with all PCI devices needing to arbitrate access to the bus amongst themselves, rather, all devices are connected to a single switch with a point-to-point connection that eliminates the need for arbitration. On the level of the switching fabric are the signals then routed to the appropriate destination, in most cases the CPU unless direct point to point busmastering between different devices is allowed / requested.

Theoretical Block diagram and practical implementation of PCI-Express in Intels' new platform. Lower image courtesy of Intel

Quality of Service

In contrast to standard interrupt request lines or SCSI channels where higher ID numbers indicate higher priority of the channel and associated device, PCIe does not differentiate between the individual members of the network, however, prioritizing of transfers and accesses is possible through specific code embedded in the packet headers. This way it is possible to favor time sensitive data transfers, e.g. for video processing, over those that are not timing critical and which can be pushed back out on the level of the switch.

PCIe enables multiple concurrent transactions as opposed to the classical PCI bus where only one IRQ and, by extension, device could be active at the time. Picture courtesy of Intel

The Practical Implementation

PCIe uses lanes and each lane consists of a a sender and a receiver pair of data lines. Each pair uses low voltage differential signalling (LVDS) and operates at 2.5 GHz, which corresponds to 200 MB data transfer. Because the connectivity uses a dual simplex (also known as full duplex) connectivity, the overall bandwidth is ~ 400 MB/sec. The normal conversion or 8bit / Byte would set the total bandwidth somewhat higher, however, keep in mind that the command and data structures are embedded in the CAD packets and, therefore, according to this Intel White Paper, we are looking at a different conversion factor. 2.5 G-Transactions per second are the starting point, target frequency for future implementations is 10 GHz, which is the theoretical frequency limit of copper interconnects and which will, theoretically provide 800 MB/sec per dual simplex lane.

In the case of the new Intel 9xx chipsets, the memory controller hub connects to the I/O controller hub (ICH6) through the DMI interface with a whopping 2 GB/sec. interconnect

One interesting aspect about PCI Express is its scalablity that includes the combination of multiple lanes into a common PCIe interface. In theory, up to 64 pairs of LVDS data lines can be combined to a 32x dual simplex PCIe interface. CCurrently the highest bandwidth supported is the PCIe 16x interface to replace the AGP slot, whereas the standard PCIe slot only features PCIe 1x. Keep in mind that the 1x interface with its 200 MB/sec upstream plus 200MB/sec downstream still provides about 3 x the bandwidth of a standard PCI interface. By extension, the 16 x PCIe interface replacing the AGP will run at 3.2 GB/sec in each direction. Note that the official number given by Intel in this case is 4 GB per direction and second, which appears inflated in view of the Intel white paper cited above.

next page:      => A new Socket =>