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LOSTCIRCUITS	SHORTCUTS: A matter of 8 cores Dual Independent Buses FBDIMMs or back to the MTH FBDIMMs, Take 2 The S5000XVN Test Configuration Memory Bandwidth Latencies Intercore and cache communication DVD Shrink, & Mainconcept H.264 Futuremarks Cinebench, POV Ray TrueSpace and Render Power Power Consumption Final Thoughts Give Us Some Feedback on this Review
Intel's V8-Demo System "Octopussy"
(Review by MS, May 31, 2007)

Summary

Allegedly, somebody at Intel had a bit too much spare time on his hands and an urgent itch to build a humble desktop system from components readily available off the shelf .... On the way to the nearest computer store, the same innocent person walked by a grocery store where a robbery was in progress and, in the process got hit with a bottle of V8, or so the story goes.

Whether it is true or not, what we got from Intel is based on the X5000 chipset, using two 3.0GHz Xeon X5365 quad core CPUs and an entire battery of FBDIMMs clocked at a docile 667 MHz data rate. Arguably not a gaming system, the US$ 3400 in hardware can handle even applications as hog-ful as Microsoft's new Office 2007 suite running under Vista - without crashing. And then there were all kinds of other applications in the general fields of content creation. And Scott Wasson beat me to the punchline: "here's a Hint, it's fast" (or something like that).

Symmetric Multiprocessing and House Keeping

A few years ago, symmetric multiprocessing (SMP) or the use of several of the same processors in one system was a somewhat exotic hobby, and mostly employed in server platforms. Consumer systems could not really take advantage of more than one CPU, simply because of operating system limitations and even Linux or WindowsNT–based systems had a hard time showing off the SMP advantage since applications were primarily single-threaded. The movement towards parallel processing of several threads got jumpstarted by Intel’s introduction of HyperThreading, essentially a fake version of SMP enabled by creating logical processors and enhancing the scheduling of data over a split front end that showed itself in the best light the worse the software was written.

Intel's S5000XVN Motherboard with support for two Xeon processors and eight FBDIMMs

By now, everybody is familiar with the concept of multiple CPUs or at least multiple cores on one CPU, the applications have matured to a degree where SMP is no longer a single thread with a bit of something extra. Needless to say that not all applications are created similar, there are differences in the utilization of more than 1 or two cores, and only a handful of programs really scale with the number of CPUs.

Another issue related to SMP is the increasingly difficult management of data in the processor caches. Every addition of another processor with its own cache causes fragmentation of the memory space, that is, instead of a single memory domain where all data are visible to every processor in the system, the caches are not visible from one CPU to the other. Cache coherency or keeping track of the data that are processed and modified by each CPU is a major issue, not just with respect to avoiding double processing of the same workload and the extra cycles wasted but also with respect to avoiding double-processed results that would be faulty.

The interaction between the different CPUs and the system to keep track of who is doing what is mostly based on what might be described as a central address look-up. That is, if any unit in the system requests data from the system memory, the address at which the data are located is broadcasted to all processors and, if it matches an existing address entry on one cache, that processor returns a cache hit signal to the system with or without the addition of the “modified flag” in which case the data in the system memory are declared invalid and need to be updated by the CPU having done the modifications. Needless to say that with increasing numbers of cores, this process becomes more complicated, too.

(BX80557E6300)

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