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LOSTCIRCUITS	SHORTCUTS: A matter of 8 cores Dual Independent Buses FBDIMMs or back to the MTH FBDIMMs, Take 2 The S5000XVN Test Configuration Memory Bandwidth Latencies Intercore and cache communication DVD Shrink, & Mainconcept H.264 Futuremarks Cinebench, POV Ray TrueSpace and Render Power Power Consumption Final Thoughts Give Us Some Feedback on this Review
Intel's V8-Demo System "Octopussy"
(Review by MS, May 31, 2007)

Bandwidth Bottlenecks

The next issue with increasing numbers of CPUs in one system is that delivering the data to each of the CPUs is facing a bigger bottleneck. Intel’s host bus or system bus (often falsely described as front side bus) is a 64-bit wide interface running at quad data rate and capable of transferring 10.6 GB/sec in the latest 1333 MHz bus iteration. For a single CPU, that amount is more than sufficient, the same goes for dual cores and maybe for quad core processors. On the other hand, Intel’s multiprocessor systems have always relied on a shared bus and according to that, a dual CPU system with 4 cores on each processor would have to split that bus and its data bandwidth over a total of eight cores, leaving 1.33 GB/sec per core on average, which brings us back to the days of the i815 chipset – at least in terms of bandwidth per core. The crux in this case is not the interfacing with peripheral devices but the access of main memory that also has to use the same shared bus.

AMD’s processors have solved this problem by using integrated memory controllers on a per CPU basis, one of the reasons why there is no bottleneck for data access, in addition, each multi processor-capable CPU can access the other CPU’s memory subdomain or “node” through a HyperTransport inter-processor link.

Dual independent host bus interfaces are what keeps the data flow to the CPUs going.

Needless to say that in the absence of on-processor memory controllers, Intel’s architecture had to find another solution and the 5000P Northbridge or Memory Controller Hub (MCH) has done away with that by using dual independent host buses, thereby effectively doubling the total available data transfer rate to 21 GB/sec (at 1333 MegaTransactions/sec). Dual independent buses, on the other hand open another can of worms with respect to the inter-processor communication but this is not the topic of the article at hand.

If the combined processors can command 21 GB/sec transfers, there needs to be a source for the same bandwidth at the backend, that is, the memory needs to be able to satisfy that amount of bandwidth. The solution in this case was meant to be a highly scalable memory architecture, relying on no less than four channels with up to eight branches each in a daisy-chain configuration. Enter the FBDIMM architecture.

(BX80557E6300)

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