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LOSTCIRCUITS	SHORTCUTS: A matter of 8 cores Dual Independent Buses FBDIMMs or back to the MTH FBDIMMs, Take 2 The S5000XVN Test Configuration Memory Bandwidth Latencies Intercore and cache communication DVD Shrink, & Mainconcept H.264 Futuremarks Cinebench, POV Ray TrueSpace and Render Power Power Consumption Final Thoughts Give Us Some Feedback on this Review
Intel's V8-Demo System "Octopussy"
(Review by MS, May 31, 2007)

The FBDIMM system

Intel’s Blackford chipset uses Fully Buffered DIMMs in a four channel configuration with 8 branches each. Going down memory lane, one can’t help but notice that the FBDIMM architecture bears a strong technical similarity with Intel’s 820 (Camino) chipset from the days of the Pentium 3 paired up with the memory translator hub (MTH). The Camino chipset was Intel’s attempt to push Rambus memory into the channel, at a time when essentially no Rambus memory was available. The workaround was to pair the high-speed 16 bit serial interface with the 64-bit parallel SDRAM interface using a translator hub integrated on the motherboard to convert the serial frames into parallel commands, addresses and data. Plagued by extreme latencies and a sheer insatiable demand for power, the MTH approach was very short-lived, to be fair, partially also because of improved availability of Rambus memory at the time.

Overall, though, the MTH has been at least from a technical standpoint an interesting solution that Intel Fellow Pete McWilliams has to be credited for. The FBDIMM is more or less the brainchild of the same group but there are slight differences between then and now. Where the Camino chipset used a bi-directional bus between the memory controller and the Rambus memory system (including the MTH variety), the FBDIMM system is relying on two unidirectional buses, one dedicated 14-bit “northbound” bus for reads and one “southbound” 10-bit bus for writes, addresses and commands. Each channel is limited to 8 branches, that is 8 physical FBDIMMs. Both buses are running at 6 x of the memory frequency to compensate for the difference in bus width and use serialized data frames for signaling.

Four FBDIMMs and eight slots.

The 14 bit northbound “read” bus transmits information from the memory to the controller hub in the form of 168-bit long frames that contain only data, including 24 bits of header information and Frame CRC values. Effectively, this results in 144 data per frame bits or the equivalent of 12 bits at 6 x the clock rate of the module using a DDR signaling protocol. This is equivalent to 16 Bytes and two ECC bytes or two transfers from a standard x72 registered ECC module. In order to fill a 32 byte cacheline on the processor, two frames are required.

The 10 bit southbound bus carries CAD information, that is Commands, Addresses and Data to be written to system memory. Each data frame is 72 bit long, that is, 8 Bytes and one ECC Byte, the rest of the bandwidth is used for command and address information that are propagated from the chipset to the advanced memory buffer or short AMB. The latter is, in contrast to the earlier MTH, integrated on each memory module rather than on the motherboard itself. The net transfer rate for writes on the southbound bus is ½ of that of the northbound bus, writing out an entire cache line of 32 Bytes to memory takes 4 frames.

As mentioned above, the northbound and southbound buses are distinct interconnects and, therefore, operating in parallel to each other rather than sharing a bidirectional bus. As a result, at least on paper, the bandwidth of both buses can be added, at least for the interconnect between the AMB and the memory controller. Since the read bandwidth equals 1 x of the read bandwidth of the DRAM components and the write bandwidth equals ½ thereof, the total R/W bandwidth is 1.5x of that of a comparable DDR-X module. Beyond the AMB, that is, on the level of the memory module itself, the data buses are still bidirectional, however, because of the integration of µ-buffers inside the AMB, read and write data can be buffered intermittently to avoid contention of the data buses on the DRAM interface level.

(BX80557E6300)

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